參數(shù)資料
型號(hào)： AD6654BBCZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 74/88頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT W/6CH RSP 256CSPBGA
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 92.16M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 2.5W
電壓電源： 模擬和數(shù)字
工作溫度： -25°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 256-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 256-CSPBGA（17x17）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，單極
AD6654
Rev. 0 | Page 76 of 88
Interrupt Enable Register <15:0>
<15>: AGC5 RSSI Update Enable Bit. When this bit is set, the
AGC5 RSSI update interrupt is enabled, allowing an interrupt
to be generated when the RSSI word is updated.
When this bit is cleared, an interrupt cannot be generated for
this event. Also, see the Interrupt Status Register <15:0> section.
<14>: AGC4 RSSI Update Enable Bit. Similar to Bit <15> for
the AGC4.
<13>: AGC3 RSSI Update Enable Bit. Similar to Bit <15> for
the AGC3.
<12>: AGC2 RSSI Update Enable Bit. Similar to Bit <15> for
the AGC2.
<11>: AGC1 RSSI Update Enable Bit. Similar to Bit <15> for
the AGC1.
<10>: AGC0 RSSI Update Enable Bit. Similar to Bit <15> for
the AGC0.
<9>: Channel 5 Data Ready Enable Bit. When this bit is set, the
Channel 5 data ready interrupt is enabled, allowing an interrupt
to be generated when Channel 5 BIST signature registers are
updated. When this bit is cleared, an interrupt cannot be
generated for this event.
<8>: Channel 4 Data Ready Enable Bit. Similar to Bit <9> for
Channel 4.
<7>: Channel 3 Data Ready Enable Bit. Similar to Bit <9> for
Channel 3.
<6>: Channel 2 Data Ready Enable Bit. Similar to Bit <9> for
Channel 2.
<5>: Channel 1 Data Ready Enable Bit. Similar to Bit <9> for
Channel 1.
<4>: Channel 0 Data Ready Enable Bit. Similar to Bit <9> for
Channel 0.
<3>: Reserved. This bit must be written with Logic 0.
<2>: ADC Port Power Monitoring Enable Bit. When this bit is
set to Logic 1, the ADC port power monitoring interrupt is
enabled, allowing an interrupt to be generated when ADC port
power monitoring registers are updated. When set to Logic 1,
the ADC port power monitoring interrupt is disabled.
<1>: Reserved. This bit must be written with Logic 0.
<0>: Reserved. This bit must be written with Logic 0.
INPUT PORT REGISTER MAP
ADC Input Control Register <27:0>
These bits are general control bits for the ADC input logic.
<27>: PN Active Bit. When this bit is set, the pseudorandom
number generator is active. When this bit is cleared, the PN
generator is disabled and the seed is set to its default value.
<26>: EXP Lock Bit. When this bit is set along with the PN
active bit, then the EXP signal for pseudorandom input is
locked to 000 (giving full-scale input). When this bit is cleared,
EXP bits for pseudorandom input are randomly generated input
data bits.
<25> Reserved. This bit must be written with Logic 0.
<24> Reserved. This bit must be written with Logic 0.
<23:20>: Channel 5 Cross Bar Mux Select Bits. These bits select
the source of input data for Channel 5. See Table 30.
Table 30. Input Data Source Selection
Cross Bar Mux Select Bits
Configuration
0010
ADC port drives input (real)
0100
PN sequence drives input (real)
<19>: Reserved. This bit must be written with Logic 0.
<18:16>: Channel 4 Cross Bar Mux Select Bits. Similar to bits
<22:20>, but for Channel 4.
<15>: Reserved. This bit must be written with Logic 0.
<14:12>: Channel 3 Cross Bar Mux Select Bits. Similar to
Bits <22:20> for Channel 3.
<11>: Reserved. This bit must be written with Logic 0.
<10:8>: Channel 2 Cross Bar Mux Select Bits. Similar to
Bits <22:20> for Channel 2.
<7>: Reserved. This bit must be written with Logic 0.
<6:4>: Channel 1 Cross Bar Mux Select Bits. Similar to
Bits <22:20> for Channel 1.
<3>: Reserved. This bit must be written with Logic 0.
<2:0>: Channel 0 Cross Bar Mux Select Bits. Similar to
Bits <22:20> for Channel 0.
ADC CLK Control Register <11:0>.
These bits control the ADC clocks and internal PLL clock.
<11>: Reserved. This bit must be written with Logic 0.
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