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參數(shù)資料
| 型號： | AD6650 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Diversity IF to Baseband GSM/EDGE Narrowband Receiver |
| 中文描述： | 多樣性IF到基帶的GSM / EDGE窄帶接收器 |
| 文件頁數(shù)： | 24/28頁 |
| 文件大小： | 594K |
| 代理商： | AD6650 |
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Preliminary Technical Data
outputs, meaning that they can drive a logic low, but not a
logic high. The pins tri-state to indicate a logic-high and this
is pulled high on the bus by external pull-up resistors to
provide a logic high to the other devices on the bus. For a
single-master, single-slave configuration, a 2.2 k-ohm
resistor should be sufficient on each of the I
2
C lines.
Stable data is transferred on SDA when SCL is high,
meaning that SDA can only be changed when SCL is low. If
SDA transitions while SCL is high, this indicates to the
AD6650 that a new transfer is being initiated on the I
2
C bus.
A start condition from the master initiates a transfer between
I
2
C devices and a stop condition ends one. A START
condition is signaled by transitioning the SDA line from
high to low while SCL is high and a transition from low to
high while SCL is high indicates a STOP condition.
AD6650
REV. PrJ 02/27/2003
24
Acknowledge (ACK) is obligatory in I
2
C, so the receiver
must send an acknowledge back to the transmitter after each
byte is transferred. The master generates the acknowledge-
related clock pulse after a given byte is transmitted and
releases the SDA line. The receiver must pull the SDA line
to a stable low before the high period of the extra clock
pulse to signal receipt of the transmitted byte.
I
2
C Access
Once a start condition has been generated, the master must
transmit the AD6650 ’s 1-byte device ID and a read/write bit
to indicate that the rest of the access to follow is intended for
it (the read/write bit and the LSB of the ID are xor ’ed
together to create one byte). The I
2
C device ID of the
AD6650 is 0010 0000 or 20 (hex). Next, the master must
transmit the instruction byte to the AD6650 indicating the
type of access to the EIR.
Bit
Comment:
7
Read/Write
6
x
5
SI[2]
4
SI[1]
3
SI[0]
2
A[2]
1
A[1]
0
A[0]
Table xx. I
2
C Instruction Byte
Each instruction byte indicates whether the EIR is being
written or read (R/Wn), which serial instruction (SI [2:0 ]) is
being executed and which register (A [2:0 ]), if appropriate,
is being accessed. The serial instruction is decoded
according to the following table.
Read/Write
SI[2:0]
0
000
Function
Write 1 byte: A[2:0] determines
EIR address
Write 2 bytes: ACR and CAR
Write 2 bytes: CAR and DR0
Write 3 bytes: ACR, CAR and
DR0
Write 4 bytes: ACR, CAR, DR1
and DR0
Write 5 bytes: ACR, CAR,
DR2, DR1, and DR0
Write 8 bytes: All EIR
addresses, ACR to DR0
Write 3 bytes: DR2, DR1, and
DR0
Read 1 byte: A[2:0] determines
EIR address
Write 2 bytes: ACR and CAR
Write 1 byte: CAR; then read 1
byte: DR0
Write 2 bytes: ACR then CAR;
then read 1 byte: DR0
Write 2 bytes: ACR then CAR;
then read 2 bytes: DR0 then
DR1
Write 2 bytes: ACR then CAR;
then read 3 bytes: DR0, DR1,
then DR2
Read 8 bytes: all EIR addresses
DR0 to ACR
Read 3 bytes: DR0, DR1, then
DR2
Table xx. I
2
C Instructions
0
0
0
001
010
011
0
100
0
101
0
110
0
111
1
000
1
1
001
010
1
011
1
100
1
101
1
110
1
111
After the instruction byte, the appropriate data must be
written to or read from the EIR. Finally, a STOP condition is
sent to end the transfer.
Pin Multiplexing
Since the programming modes of the AD6650 are all
mutually exclusive, the pins used for each mode are all
multiplexed together and are named after their microport
function. For I
2
Cmode, the SCL pin is the DSn pin in
microport mode and the SDA pin is the DTACKn pin in
microport mode.
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