參數(shù)資料
型號(hào): AD6645ASVZ-80
廠商: Analog Devices Inc
文件頁數(shù): 23/24頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 80MSPS 52TQFP
設(shè)計(jì)資源: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
標(biāo)準(zhǔn)包裝: 1
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 4
功率耗散(最大): 1.75W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 52-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 52-TQFP-EP(10x10)
包裝: 托盤
輸入數(shù)目和類型: 1 個(gè)差分,雙極
AD6645
Rev. D | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. DNC = DO NOT CONNECT.
2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND.
PIN 1
IDENTIFIER
AD6645
TOP VIEW
(Not to Scale)
1
DVCC
2
GND
3
VREF
4
GND
5
ENCODE
6
ENCODE
7
GND
8
AVCC
9
AVCC
10
GND
11
14
AIN
12
AIN
13
GND
AV
CC
15
GN
D
16
AV
CC
17
GN
D
18
AV
CC
19
GN
D
20
C1
21
GN
D
22
AV
CC
23
GN
D
24
C2
25
GN
D
26
AV
CC
27
GND
28
AVCC
29
GND
30
AVCC
31
DNC
32
OVR
33
DVCC
34
GND
35
DMID
36
D0 (LSB)
37
40
D1
38
D2
39
D3
D4
41
D5
42
GN
D
43
DV
CC
44
D6
45
D7
46
D8
47
D9
48
D10
49
D11
50
D12
51
D13
(
M
S
B
)
52
DRY
02
64
7-
0
03
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin Number
Mnemonic
Description
1, 33, 43
DVCC
3.3 V Power Supply (Digital) Output Stage Only.
2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25,
27, 29, 34, 42
GND
Ground.
3
VREF
2.4 V Reference. Bypass to ground with a 0.1 μF microwave chip capacitor.
5
ENCODE
Encode Input. Conversion initiated on rising edge.
6
ENCODE
Complement of ENCODE, Differential Input.
8, 9, 14, 16, 18, 22, 26, 28, 30
AVCC
5 V Analog Power Supply.
11
AIN
Analog Input.
12
AIN
Complement of AIN, Differential Analog Input.
20
C1
Internal Voltage Reference. Bypass to ground with a 0.1 μF chip capacitor.
24
C2
Internal Voltage Reference. Bypass to ground with a 0.1 μF chip capacitor.
31
DNC
Do not connect this pin.
32
OVR
Overrange Bit. A logic level high indicates analog input exceeds ±FS.
35
DMID
Output Data Voltage Midpoint. Approximately equal to (DVCC)/2.
36
D0 (LSB)
Digital Output Bit (Least Significant Bit); Twos Complement.
37 to 41, 44 to 50
D1 to D5, D6 to D12
Digital Output Bits in Twos Complement.
51
D13 (MSB)
Digital Output Bit (Most Significant Bit); Twos Complement.
52
DRY
Data-Ready Output.
53 (EPAD)
Exposed Paddle (EPAD)
Exposed Pad. Connect the exposed pad to GND.
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