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參數(shù)資料
| 型號(hào)： | AD650SD |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 385K |
| 描述： | IC V-F/F-V CONV 1MHZ 14-CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 電壓至頻率和頻率至電壓 |
| 頻率 - 最大： | 1MHz |
| 全量程： | ±150ppm/°C |
| 線性： | ±0.1% |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-CDIP |
| 包裝： | 管件 |
AD650
Data Sheet
Rev. E | Page 8 of 20
The positive input voltage develops a current (IIN = VIN/RIN) that
charges the integrator capacitor CINT. As charge builds up on
CINT, the output voltage of the integrator ramps downward
towards ground. When the integrator output voltage (Pin 1)
crosses the comparator threshold (0.6 V) the comparator
triggers the one shot, whose time period, t
OS
is determined by
the one-shot capacitor C
OS
.
Specifically, the one-shot time period is
sec
10
0
.
3
F
/
sec
10
8
.
6
7
3
?/DIV>
+
?/DIV>
?/DIV>
=
OS
OS
C
(1)
The reset period is initiated as soon as the integrator output
voltage crosses the comparator threshold, and the integrator
ramps upward by an amount
(
)
IN
INT
OS
OS
I
C
t
dt
dV
t
V
=
?/DIV>
=
mA
1
(2)
After the reset period has ended, the device starts another
integration period, as shown in Figure 8, and starts ramping
downward again. The amount of time required to reach the
comparator threshold is given as
( )
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
=
=
1
mA
1
mA
1
1
IN
OS
INT
N
IN
INT
OS
I
t
C
I
I
C
t
dt
dV
V
(3)
The output frequency is now given as
F
C
R
V
A
F
t
I
T
t
OS
IN
IN
OS
IN
OS
OUT
11
1
10
4
.
4
/
Hz
15
.
mA
1
1
?/DIV>
+
?/DIV>
=
?/DIV>
=
+
=
(4)
Note that C
INT
, the integration capacitor, has no effect on the
transfer relation, but merely determines the amplitude of the
sawtooth signal out of the integrator.
One-Shot Timing
A key part of the preceding analysis is the one-shot time period
given in Equation 1. This time period can be broken down into
approximately 300 ns of propagation delay and a second time
segment dependent linearly on timing capacitor C
OS
. When the
one shot is triggered, a voltage switch that holds Pin 6 at analog
ground is opened, allowing that voltage to change. An internal
0.5 mA current source connected to Pin 6 then draws its
current out of COS, causing the voltage at Pin 6 to decrease
linearly. At approximately 3.4 V, the one shot resets itself,
thereby ending the timed period and starting the V/F
conversion cycle over again. The total one-shot time period can
be written mathematically as
DELAY
GATE
DISCHARGE
OS
OS
T
I
C
V
+
=
(5)
substituting actual values quoted in Equation 5,
sec
10
300
A
10
5
.
0
V
4
.
3
9
3
?/DIV>
+
?/DIV>
?/DIV>
=
OS
OS
C
(6)
This simplifies into the timed period equation (see Equation 1).
COMPONENT SELECTION
Only four component values must be selected by the user. These
are input resistance R
IN
, timing capacitor C
OS
, logic resistor R2,
and integration capacitor C
INT
. The first two determine the
input voltage and full-scale frequency, while the last two are
determined by other circuit considerations.
Of the four components to be selected, R2 is the easiest to
define. As a pull-up resistor, it should be chosen to limit the
current through the output transistor to 8 mA if a TTL
maximum V
OL
of 0.4 V is desired. For example, if a 5 V logic
supply is used, R2 should be no smaller than 5 V/8 mA or
625 ? A larger value can be used if desired.
R
IN
and C
OS
are the only two parameters available to set the full-
scale frequency to accommodate the given signal range. The swing
variable that is affected by the choice of RIN and COS is nonlinearity.
The selection guides of Figure 9 and Figure 10 show this quite
graphically. In general, larger values of COS and lower full-scale
input currents (higher values of R
IN
) provide better linearity. In
Figure 10, the implications of four different choices of R
IN
are
shown. Although the selection guide is set up for a unipolar
configuration with a 0 V to 10 V input signal range, the results
can be extended to other configurations and input signal ranges.
For a full-scale frequency of 100 kHz (corresponding to 10 V
input), among the available choices RIN = 20 k& and COS = 620 pF
gives the lowest nonlinearity, 0.0038%. In addition, the highest
frequency that gives the 20 ppm minimum nonlinearity is
approximately 33 kHz (40.2 k?and 1000 pF).
For input signal spans other than 10 V, the input resistance
must be scaled proportionately. For example, if 100 k?is called
out for a 0 V to 10 V span, 10 k& would be used with a 0 V to 1 V
span, or 200 k?with a ?0 V bipolar connection.
The last component to be selected is the integration capacitor
C
INT
. In almost all cases, the best value for C
INT
can be calculated
using the equation
(
)
minimum
pF
1000
sec
/
10
4
MAX
INT
f
F
=
(7)
When the proper value for C
INT
is used, the charge balance
architecture of the AD650 provides continuous integration
of the input signal, therefore, large amounts of noise and
interference can be rejected. If the output frequency is
measured by counting pulses during a constant gate period,
the integration provides infinite normal-mode rejection for
frequencies corresponding to the gate period and its harmonics.
However, if the integrator stage becomes saturated by an
excessively large noise pulse, then the continuous integration of
the signal is interrupted, allowing the noise to appear at the output.
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