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| 型號(hào)： | AD640JPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP LOG 2.3MA 20PLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 對(duì)數(shù) |
| 電路數(shù)： | 1 |
| -3db帶寬： | 350MHz |
| 電流 - 輸入偏壓： | 7µA |
| 電壓 - 輸入偏移： | 50µV |
| 電流 - 電源： | 35mA |
| 電流 - 輸出 / 通道： | 2.3mA |
| 電壓 - 電源，單路/雙路(±)： | ±4.5 V ~ 7.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 20-PLCC（9x9） |
| 包裝： | 管件 |
AD640
REV. C
–16–
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
be increased and U3 can be replaced by a low speed op amp.
Figure 31 shows typical performance of this converter.
10 Hz–100 kHz Converter with 95 dB Dynamic Range
To increase the dynamic range it is necessary to reduce the
bandwidth by the inclusion of a low-pass filter at the signal
interface between U1 and U2 (Figure 32). To provide operation
down to low frequencies, dc coupling is used at the interface
between AD640s and the input offset is nulled by a feedback
circuit.
Using values of 0.02
F in the interstage filter formed by capaci-
tors C1 and C2, the hf corner occurs at about 100 kHz. U3
(AD712) forms a 4-pole 35 Hz low-pass filter. This provides
operation to signal frequencies below 20 Hz. The filter response
is not critical, allowing the use of an electrolytic capacitor to
form one of the poles.
R1 is restricted to 50
by the compliance at Pin 14, so C3
needs to be large to form a 5 ms time constant. A tantalum
capacitor is used (note polarity). The output of U3a is scaled
+1 V per decade, and the X2 gain of U3b raises this to +2 V per
decade, or +100 mV/dB. The differential offset at the output of
U2 is low-pass filtered by R6/C7 and R7/C8 and buffered by
voltage followers U4a and U4b. The 16s open loop time constant
translates to a closed loop high-pass corner of 10 Hz. (This
high-pass filter is only operative for very small inputs; see page
13.) Figure 33 shows the performance for square wave inputs.
Since the attenuator is used, the upper end of the dynamic
range now extends to +6 dBV and the intercept is at –82 dBV.
The noise limited dynamic range is over 100 dB, but in practice
spurious signals at the input will determine the achievable range.
INPUT AMPLITUDE AT 10kHz
–1
–90
31.6
LOG
OUTPUT
FROM
CIRCUIT
OF
FIGURE
32
–
V
0
1
2
3
4
5
6
7
8
9
–80
100
–70
316
–60
1m
–50
3.16m
–40
10m
–30
31.6m
–20
100m
–10
316m
0
1
10
3.16
dBV
V
–2
0
2
ERROR
FROM
IDEAL
TRANSFER
FUNCTION
–
dB
Figure 33. Logarithmic Output and Nonlinearity for Circuit
of Figure 32, for a Square Wave Input at f = 10 kHz
C1297b–0–12/99
(rev.
C)
PRINTED
IN
U.S.A.
20-Lead Ceramic DIP (D) Package
20
1
10
11
0.300 (7.62)
0.280 (7.11)
PIN 1
0.320 (8.13)
0.300 (7.62)
0.430 (10.16)
SEATING
PLANE
0.020 (0.51)
0.015 (0.38)
1.010 (25.65)
0.990 (25.15)
0.095
(2.41)
0.210 (5.33)
0.150 (3.81)
0.054 (1.37)
0.040 (1.01)
0.10
(2.54)
0.085
(2.16)
0.012 (0.30)
0.008 (0.20)
0.300 (7.62)
20-Terminal Ceramic LCC (E) Package
1
20
4
9
8
13
19
14
3
18
PIN 1
INDEX
BOTTOM VIEW
0.20
45
(0.51
45 )
REF
0.025
0.003
(0.635
0.075)
0.050
(1.27)
0.040
45
(1.02
45 )
REF 3 PLCS
0.350
0.008
(8.89
0.20)
SQ
0.082
0.018
(2.085
0.455)
20-Lead Plastic DIP (N) Package
20
110
11
PIN 1
0.250
(6.350)
TYP
1.070 (27.18)
0.310
(7.874)
TYP
0.014 (0.356)
0.008 (0.203)
0.180
(4.572)
MAX
0.300 (7.62)
TYP
15
0
SEATING
PLANE
0.045 (1.143)
0.025 (0.635)
0.021 (0.533)
0.015 (0.381)
0.100
(2.54)
TYP
0.125 (3.18)
MIN
0.033
(0.838)
TYP
20-Lead PLCC (P) Package
0.017
0.004
(0.432
0.101)
0.029
0.003
(0.737
0.076)
0.025 (0.64) MIN
0.060 (1.53) MIN
0.020 (0.51) MIN
R
0.035
0.01
(0.89
0.25)
0.173
0.008
(4.385
0.185)
0.105
0.015
(2.665
0.375)
3
PIN 1
IDENTIFIER
4
19
18
8
9
14
13
TOP VIEW
(PINS DOWN)
0.020 (0.51)
MAX
0.050
(1.27)
0.045
0.003
(1.143
0.076)
0.353
0.003
(8.966
0.076)
SQ
0.390
0.005
(9.905
0.125)
SQ
0.020
(0.51)
MAX
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| AD640JPZ-REEL7 | 功能描述:IC AMP LOG 2.3MA 20PLCC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 放大器類型:J-FET 電路數(shù):2 輸出類型:- 轉(zhuǎn)換速率:3.5 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:30pA 電壓 - 輸入偏移:2000µV 電流 - 電源:200µA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 |
| AD640T | 制造商:AD 制造商全稱:Analog Devices 功能描述:DC-Coupled Demodulating 120 MHz Logarithmic Amplifier |
| AD640TCHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:DC-Coupled Demodulating 120 MHz Logarithmic Amplifier |
| AD640TD | 制造商:AD 制造商全稱:Analog Devices 功能描述:DC-Coupled Demodulating 120 MHz Logarithmic Amplifier |
| AD640TD/883B | 功能描述:對(duì)數(shù)放大器 I.C. LOG AMP IC RoHS:否 制造商:Texas Instruments 通道數(shù)量:3 帶寬:3 dB 共模抑制比（最小值）: 輸入補(bǔ)償電壓:+/- 7 mV 輸入電壓范圍（最大值）:5.5 V 工作電源電壓:4.5 V to 5.5 V 電源電流:+/- 15 mA 工作溫度范圍:- 40 C to +85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-16 封裝:Reel |
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