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參數(shù)資料
| 型號(hào)： | AD6315LF |
| 英文描述： | 1/4- to 1/12 Duty VFD Controller/Driver |
| 中文描述： | 1/4- 1 / 12的稅VFD顯示控制器/驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 243K |
| 代理商： | AD6315LF |
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AD6315
1/4- to 1/12 Duty VFD Controller/Driver
Pin Descriptions
Symbol
Anachip Corp.
www.anachip.com.tw
Rev. A5 Dec 29, 2003
2/16
Name
No.
Description
D
IN
Data input
7
Input serial data at rising edge of shift clock,
starting from the low order bit.
Output serial data at the falling edge of the
shift clock, starting from low order bit. This is
N-ch open-drain output pin.
Initializes serial interface at the rising or
falling edge of the AD6315. It then waits for
reception of a command. Data input after
STB falling is processed as a command.
While command data is processed, current
processing is stopped, and the serial
interface is initialized. While STB is high, CLK
is ignored.
Reads serial data at the rising edge, and
outputs data at the falling edge.
Connect resistor in between this pin and Vss to set
up the oscillation frequency.
14 to 29 source)
39 to 42 Grid output pins
31 to 38 driving.
1 to 4
CMOS output
D
OUT
Data output
6
STB
Strobe
9
CLK
Clock input
8
OSC
Oscillator pin
5
Seg
1
/KS
1
to
Seg
16
/KS
16
Grid
1
to Grid
4
Seg
17
/Grid
12
to
Seg
24
/Grid
5
LED
1
to LED
4
High-voltage output (Segment)
High-voltage output (Grid)
High-voltage output
(Segment/grid)
LED output
KEY
1
, KEY
2
Key data input
10, 11
Data input to these pins is latched at the end
of the display cycle.
V
DD
Logic power
13, 43
Logic power supply
V
SS
Logic ground
12, 44
Connect this pin to system GND.
V
EE
Pull-down level
30
Driver power supply
Ordering Information
AD6315X X X
Packing
Blank : Tray
Q: QFP-44L
L : LQFP-44L
Package
Lead
Blank: Normal
F: Lead Free
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