參數(shù)資料
型號(hào): AD628ARZ
廠商: Analog Devices Inc
文件頁數(shù): 8/21頁
文件大小: 0K
描述: IC AMP PGA DIFF PREC 8SOIC
產(chǎn)品培訓(xùn)模塊: Top Five Instrumentation Amplifier Problems
標(biāo)準(zhǔn)包裝: 98
放大器類型: 電流檢測(cè)
電路數(shù): 1
轉(zhuǎn)換速率: 0.3 V/µs
-3db帶寬: 600kHz
電流 - 輸入偏壓: 1.5nA
電壓 - 輸入偏移: 150µV
電流 - 電源: 1.6mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 36 V,±2.25 V ~ 18 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 管件
產(chǎn)品目錄頁面: 771 (CN2011-ZH PDF)
AD628
Rev. G | Page 15 of 20
THEORY OF OPERATION
The AD628 is a high common-mode voltage difference
amplifier, combined with a user-configurable output amplifier
(see Figure 28 and Figure 29). Differential mode voltages in
excess of 120 V are accurately scaled by a precision 11:1 voltage
divider at the input. A reference voltage input is available to the
user at Pin 3 (VREF). The output common-mode voltage of the
difference amplifier is the same as the voltage applied to the
reference pin. If the uncommitted amplifier is configured for
gain, connect Pin 3 to one end of the external gain resistor to
establish the output common-mode voltage at Pin 5 (OUT).
The output of the difference amplifier is internally connected to
a 10 kΩ resistor trimmed to better than ±0.1% absolute accuracy.
The resistor is connected to the noninverting input of the
output amplifier and is accessible at Pin 4 (CFILT). A capacitor
can be connected to implement a low-pass filter, a resistor can
be connected to further reduce the output voltage, or a clamp
circuit can be connected to limit the output swing.
The uncommitted amplifier is a high open-loop gain, low offset,
low drift op amp, with its noninverting input connected to the
internal 10 kΩ resistor. Both inputs are accessible to the user.
Careful layout design has resulted in exceptional common-
mode rejection at higher frequencies. The inputs are connected
to Pin 1 (+IN) and Pin 8 (IN), which are adjacent to the power
pins, Pin 2 (VS) and Pin 7 (+VS). Because the power pins are at
ac ground, input impedance balance and, therefore, common-
mode rejection are preserved at higher frequencies.
+IN
–IN
+IN
–IN
A2
A1
+IN
–IN
100k
10k
VREF
10k
OUT
G = +0.1
CFILT
RG
02
99
2-
0
28
5
6
4
3
1
8
Figure 28. Simplified Schematic
+VS
+IN
–IN
–VS
A2
+IN
–IN
100k
10k
VREF
REFERENCE
VOLTAGE
10k
AD628
OUT
G = +0.1
RG
REXT3
CFILT
REXT2
REXT1
+IN
–IN
A1
5
3
2
1
8
6
02
99
2-
0
29
4
7
Figure 29. Circuit Connections
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