參數(shù)資料
型號: AD603ARZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 11/25頁
文件大?。?/td> 0K
描述: IC AMP VGA 90MHZ LN 50MA 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: X-AMP®
放大器類型: 可變增益
電路數(shù): 1
轉(zhuǎn)換速率: 275 V/µs
-3db帶寬: 90MHz
電流 - 輸入偏壓: 200nA
電流 - 電源: 12.5mA
電流 - 輸出 / 通道: 50mA
電壓 - 電源,單路/雙路(±): 9.5 V ~ 12.6 V,±4.75 V ~ 6.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 帶卷 (TR)
配用: AD603-EVALZ-ND - BOARD EVALUATION FOR AD603
AD603
Data Sheet
Rev. K | Page 18 of 24
APPLICATIONS INFORMATION
A LOW NOISE AGC AMPLIFIER
Figure 49 shows the ease with which the AD603 can be
connected as an AGC amplifier. The circuit illustrates many of
the points previously discussed: it uses few parts, has linear-in-
dB gain, operates from a single supply, uses two cascaded amplifiers
in sequential gain mode for maximum SNR, and an external
resistor programs each gain of the amplifier. It also uses a
simple temperature-compensated detector.
The circuit operates from a single 10 V supply. Resistors R1, R2,
R3, and R4 bias the common pins of A1 and A2 at 5 V. The
common pin is a low impedance point and must have a low
impedance path to ground, provided here by the 100 μF tantalum
capacitors and the 0.1 μF ceramic capacitors.
The cascaded amplifiers operate in sequential gain. Here, the
offset voltage between Pin 2 (GNEG) of A1 and A2 is 1.05 V
(42.14 dB × 25 mV/dB), provided by a voltage divider consisting of
Resistors R5, R6, and R7. Using standard values, the offset is not
exact, but it is not critical for this application.
The gain of both A1 and A2 is programmed by Resistors R13
and R14, respectively, to be about 42 dB; therefore, the maximum
gain of the circuit is twice that, or 84 dB. The gain control range
can be shifted up by as much as 20 dB by appropriate choices of
R13 and R14.
The circuit operates as follows:
A1 and A2 are cascaded.
Capacitor C1 and the 100 Ω of resistance at the input of A1
form a time constant of 10 μs.
C2 blocks the small dc offset voltage at the output of A1
(which might otherwise saturate A2 at its maximum gain)
and introduces a high-pass corner at about 16 kHz,
eliminating low frequency noise.
A half-wave detector is used, based on Q1 and R8. The current
into capacitor, CAV, is the difference between the collector
current of Q2 (biased to be 300 μA at 300 K, 27°C) and the
collector current of Q1, which increases with the amplitude
of the output signal.
The automatic gain control voltage, VAGC, is the time integral
of this error current. For VAGC (and thus the gain) to remain
insensitive to short-term amplitude fluctuations in the output
signal, the rectified current in Q1 must, on average, exactly
balance the current in Q2. If the output of A2 is too small to
do this, VAGC increases, causing the gain to increase until Q1
conducts sufficiently.
Consider the case where R8 is zero and the output voltage VOUT
is a square wave at, for example, 455 kHz, which is well above
the corner frequency of the control loop.
C2
0.1F
R1 3
2.49k
10V
5.5V
6.5V
+
R2
2.49k
C32
100F
C4
0.1F
R1
2.49k
RT1
100
J1
R6
1.05k
R5
5.49k
R7
3.48k
10V
AGC LINE
CAV
0.1F
THIS CAPACITOR SETS
AGC TIME CONSTANT
VAGC
R9
1.54k
R8
806
Q1
2N3904
Q2
2N3906
R1 0
1.24k
R11
3.83k
5V
R1 2
4.99k
C11
0.1F
C9
0.1F
10V
J2
C10
0.1F
10V
C7
0.1F
C1
0.1F
A1
AD603
1
2
3
7
4
8
6
5
R1 4
2.49k
R4
2.49k
C52
100F
C6
0.1F
R3
2.49k
10V
C8
0.1F
A2
AD603
1
2
3
7
4
8
6
5
1V OFFSET FOR
SEQUENTIAL GAIN
1 RT PROVIDES A 50 INPUT IMPEDANCE.
2 C3 AND C5 ARE TANTALUM.
00
53
9-
0
47
Figure 49. A Low Noise AGC Amplifier
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