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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AD603AR
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 6/25闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC AMP VGA 90MHZ LN 50MA 8SOIC
妯欐簴鍖呰锛� 1
绯诲垪锛� X-AMP®
鏀惧ぇ鍣ㄩ鍨嬶細 鍙畩澧炵泭
闆昏矾鏁�(sh霉)锛� 1
杞夋彌閫熺巼锛� 275 V/µs
-3db甯跺锛� 90MHz
闆绘祦 - 杓稿叆鍋忓锛� 200nA
闆绘祦 - 闆绘簮锛� 12.5mA
闆绘祦 - 杓稿嚭 / 閫氶亾锛� 50mA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 9.5 V ~ 12.6 V锛�±4.75 V ~ 6.3 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 8-SO
鍖呰锛� 绠′欢
閰嶇敤锛� AD603-EVALZ-ND - BOARD EVALUATION FOR AD603
Data Sheet
AD603
Rev. K | Page 13 of 24
SCALING
REFERENCE
VG
GAIN-
CONTROL
INTERFACE
AD603
PRECISION PASSIVE
INPUT ATTENUATOR
FIXED-GAIN
AMPLIFIER
*NOMINAL VALUES.
R-2R LADDER NETWORK
VPOS
VNEG
GPOS
GNEG
VINP
COMM
0dB
鈥�6.02dB 鈥�12.04dB 鈥�18.06dB 鈥�24.08dB 鈥�30.1dB 鈥�36.12dB 鈥�42.14dB
R
RR
RRR
R
2R
R
20*
694*
6.44k*
VOUT
FDBK
00
53
9-
0
29
8
6
1
2
5
7
4
3
Figure 31. Simplified Block Diagram
THE GAIN CONTROL INTERFACE
The attenuation is controlled through a differential, high
impedance (50 M惟) input, with a scaling factor that is laser-
trimmed to 40 dB per volt, that is, 25 mV/dB. An internal band
gap reference ensures stability of the scaling with respect to
supply and temperature variations.
When the differential input voltage VG = 0 V, the attenuator
slider is centered, providing an attenuation of 21.07 dB. For the
maximum bandwidth range, this results in an overall gain of
10 dB (= 21.07 dB + 31.07 dB). When the control input is
500 mV, the gain is lowered by +20 dB (= 0.500 V 脳 40 dB/V)
to 10 dB; when set to +500 mV, the gain is increased by
+20 dB to +30 dB. When this interface is overdriven in either
direction, the gain approaches either 11.07 dB (= 42.14 dB +
+31.07 dB) or 31.07 dB (= 0 + 31.07 dB), respectively. The only
constraint on the gain control voltage is that it be kept within
the common-mode range (1.2 V to +2.0 V assuming +5 V
supplies) of the gain control interface.
The basic gain of the AD603 can therefore be calculated by
Gain (dB) = 40 VG +10
(1)
where VG is in volts. When Pin 5 and Pin 7 are strapped (see the
section), the gain becomes
Gain (dB) = 40 VG + 20 for 0 to +40 dB
and
Gain (dB) = 40 VG + 30 for +10 to +50 dB
(2)
The high impedance gain control input ensures minimal
loading when driving many amplifiers in multiple channel
or cascaded applications. The differential capability provides
flexibility in choosing the appropriate signal levels and
polarities for various control schemes.
For example, if the gain is to be controlled by a DAC providing
a positive-only, ground-referenced output, the gain control low
(GNEG) pin should be biased to a fixed offset of 500 mV to set
the gain to 10 dB when gain control high (GPOS) is at zero,
and to 30 dB when at 1.00 V.
It is a simple matter to include a voltage divider to achieve other
scaling factors. When using an 8-bit DAC having an FS output
of 2.55 V (10 mV/bit), a divider ratio of 2 (generating 5 mV/bit)
results in a gain-setting resolution of 0.2 dB/bit. The use of such
offsets is valuable when two AD603s are cascaded, when
various options exist for optimizing the signal-to-noise profile,
as is shown in the Sequential Mode (Optimal SNR) section,
PROGRAMMING THE FIXED-GAIN AMPLIFIER
USING PIN STRAPPING
Access to the feedback network is provided at Pin 5 (FDBK).
The user may program the gain of the output amplifier of the
AD603 using this pin, as shown in Figure 32, Figure 33, and
Figure 34. There are three modes: in the default mode, FDBK
is unconnected, providing the range +9 dB/+51 dB; when VOUT
and FDBK are shorted, the gain is lowered to 11 dB/+31 dB;
and, when an external resistor is placed between VOUT and
FDBK, any intermediate gain can be achieved, for example,
1 dB/+41 dB. Figure 35 shows the nominal maximum gain vs.
external resistor for this mode.
GPOS
GNEG
VINP
COMM
VPOS
VOUT
VNEG
FDBK
AD603
VC1
VC2
VIN
VPOS
VOUT
VNEG
00
53
9-
0
30
8
7
6
5
1
2
3
4
Figure 32. 10 dB to +30 dB; 90 MHz Bandwidth
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