參數(shù)資料
型號(hào)： AD5764RBSUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/32頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT QUAD VOUT 32-TQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： AD5764(R), AD5744R Product Change 04/Sept/2009
設(shè)計(jì)資源： High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5764 (CN0006)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 8µs
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 雙 ±
功率耗散（最大）： 275 mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-TQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 托盤(pán)
輸出數(shù)目和類(lèi)型： 4 電壓，雙極
產(chǎn)品目錄頁(yè)面： 784 (CN2011-ZH PDF)
AD5764R
Data Sheet
Rev. D | Page 26 of 32
OFFSET REGISTER
The offset register is addressed by setting the three REG bits to 101. The DAC address bits select the DAC channel with which the data
transfer takes place (see Table 10). The AD5764R offset register is an 8-bit register that allows the user to adjust the offset of each channel
by 16 LSBs to +15.875 LSBs in steps of one-eighth LSB, as shown in Table 18 and Table 19. The offset register coding is twos complement.
Table 18. Programming the Offset Register
REG2
REG1
REG0
A2
A1
A0
DB15 to DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
DAC address
Don’t care
OF7
OF6
OF5
OF4
OF3
OF2
OF1
OF0
Table 19. Offset Register Options
Offset Adjustment
OF7
OF6
OF5
OF4
OF3
OF2
OF1
OF0
+15.875 LSBs
0
1
+15.75 LSBs
0
1
0
No Adjustment (Default)
0
15.875 LSBs
1
0
1
16 LSBs
1
0
OFFSET AND GAIN ADJUSTMENT WORKED
EXAMPLE
Using the information provided in the Offset Register section,
the following worked examples demonstrate how the AD5764R
functions can be used to eliminate both offset and gain errors.
Because the AD5764R is factory calibrated, offset and gain errors
should be negligible. However, errors can be introduced by the
system within which the AD5764R is operating. For example,
a voltage reference value that is not equal to 5 V introduces
a gain error. An output range of ±10 V and twos complement
data coding are assumed.
Removing Offset Error
The AD5764R can eliminate an offset error in the range of
4.88 mV to +4.84 mV with a step size of one-eighth of a
16-bit LSB.
1.
Calculate the step size of the offset adjustment, using the
following equation:
Offset Adjust Step Size =
8
2
20
16 ×
= 38.14 V
2.
Measure the offset error by programming 0x0000 to the
data register and measuring the resulting output voltage.
For this example, the measured value is 614 V.
3.
Determine how many offset adjustment steps this value
represents, using the following equation:
Number of Steps =
V
14
.
38
V
614
=
Size
Step
Offset
Value
Offset
Measured
= 16 Steps
The offset error measured is positive; therefore, a negative
adjustment of 16 steps is required. The offset register is
eight bits wide, and the coding is twos complement.
The required offset register value can be calculated as follows:
1.
Convert the adjustment value to binary: 00010000.
2.
Convert this binary value to a negative twos complement
number by inverting all bits and adding 1: 11110000.
3.
Program this value, 11110000, to the offset register.
Note that this twos complement conversion is not necessary in
the case of a positive offset adjustment. The value to be pro-
grammed to the offset register is simply the binary representation
of the adjustment value.
Removing Gain Error
The AD5764R can eliminate a gain error at negative full-scale
output in the range of 9.77 mV to +9.46 mV with a step size of
one-half of a 16-bit LSB.
1.
Calculate the step size of the gain adjustment, using the
following equation:
Gain Adjust Step Size =
2
20
16 ×
= 152.59 V
2.
Measure the gain error by programming 0x8000 to the
data register and measuring the resulting output voltage.
The gain error is the difference between this value and 10 V.
For this example, the gain error is 1.2 mV.
3.
Determine how many gain adjustment steps this value
represents, using the following equation:
Number of Steps =
V
59
.
152
mV
2
.
1
=
Size
Step
Gain
Value
Gain
Measured
= 8 Steps
The gain error measured is negative (in terms of magnitude).
Therefore, a positive adjustment of eight steps is required. The
gain register is six bits wide, and the coding is twos complement.
The required gain register value can be determined as follows:
1.
Convert the adjustment value to binary: 001000.
2.
Program this binary number to the gain register.
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