參數(shù)資料
型號(hào)： AD5764RBSUZ-REEL7
廠商： ANALOG DEVICES INC
元件分類(lèi)： DAC
英文描述： Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
中文描述： SERIAL INPUT LOADING, 8 us SETTLING TIME, 16-BIT DAC, PQFP32
封裝： ROHS COMPLIANT, PLASTIC, MS-026ABA, TQFP-32
文件頁(yè)數(shù)： 24/32頁(yè)
文件大小： 524K
代理商： AD5764RBSUZ-REEL7
AD5764R
DATA REGISTER
The data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC channel the data transfer
is to take place (see Table 8). The data bits are in positions DB15 to DB0 for the AD5764R as shown in Table 11.
Table 11. Programming the AD5764R Data Register
REG2
REG1
REG0
A2
A1
A0
DB15
DB14
DB13
DB12
DB11
0
1
0
DAC Address
Rev. PrA | Page 24 of 32
DB10
DB9
16-Bit DAC Data
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 8). The coarse gain register is a 2-bit register and allows the user to select the output range of each DAC
as shown in Table 13.
Table 12. Programming the AD5764R Coarse Gain Register
REG2
REG1
REG0
A2
A1
0
1
1
DAC Address
A0
DB15 …. DB2
Don’t Care
DB1
CG1
DB0
CG0
Table 13. Output Range Selection
Output Range
±10 V (default)
±10.2564 V
±10.5263 V
CG1
0
0
1
CG0
0
1
0
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 8). The AD5764R fine gain register is a 6-bit register and allows the user to adjust the gain of each DAC
channel by 32 LSBs to +31 LSBs in 1 LSB steps as shown in Table 14 and Table 15. The adjustment is made to both the positive full-scale
points and the negative full-scale points simultaneously, each point being adjusted by of one step. The fine gain register coding is twos
complement.
Table 14. Programming AD5764R Fine Gain Register
REG2
REG1
REG0
A2
A1
A0
DB15:DB6
1
0
0
DAC Address
Don’t Care
DB5
FG5
DB4
FG4
DB3
FG3
DB2
FG2
DB1
FG1
DB0
FG0
Table 15. AD5764R Fine Gain Register Options
Gain Adjustment
+31 LSBs
+30 LSBs
No Adjustment (default)
31 LSBs
32 LSBs
OFFSET REGISTER
The offset register is addressed by setting the three REG bits to 101. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 8). The AD5764R offset register is an 8-bit register and allows the user to adjust the offset of each
channel by 16 LSBs to +15.875 LSBs in steps of LSB as shown in Table 16 and Table 17. The offset register coding is twos complement.
Table 16. Programming the AD5764R Offset Register
REG2
REG1
REG0
A2
A1
A0
DB15:DB8
1
0
1
DAC Address
Don’t Care
FG5
0
0
-
0
-
1
1
FG4
1
1
-
0
-
0
0
FG3
1
1
-
0
-
0
0
FG2
1
1
-
0
-
0
0
FG1
1
1
-
0
-
0
0
FG0
1
0
-
0
-
1
0
DB7
OF7
DB6
OF6
DB5
OF5
DB4
OF4
DB3
OF3
DB2
OF2
DB1
OF1
DB0
OF0
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