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參數(shù)資料
| 型號： | AD5764RASUZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 16-BIT DAC, PQFP32 |
| 封裝： | LEAD FREE, PLASTIC, MS-026ABA, TQFP-32 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 524K |
| 代理商： | AD5764RASUZ |
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AD5764R
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. PrA | Page 11 of 32
SYNC
SCLK
SDIN
SDO
CLR
LDAC
D1
D0
AGNDA
VOUTA
VOUTB
AGNDB
AGNDC
VOUTC
VOUTD
AGNDD
R
R
D
D
C
A
D
P
I
A
S
B
A
D
A
S
T
R
R
R
R
1
2
3
4
5
6
7
8
23
22
21
18
19
20
24
17
PIN 1
9
10 11
12
13
14 15
16
32
31
30
29
28
27
26
25
AD5764R
TOP VIEW
(Not to Scale)
0
Figure 6. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
1
SYNC
Description
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds
up to 30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode.
Negative Edge Triggered Input. Asserting this pin sets the DAC registers to 0x0000.
Load DAC. Logic input. This is used to update the DAC registers and consequently the analog outputs. When tied
permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during
the write cycle, the DAC input register is updated but the output update is held off until the falling edge of LDAC.
In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin must
not be left unconnected.
D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are configurable and
readable over the serial interface. When configured as inputs, these pins have weak internal pull-ups to DV
CC
.
When programmed as outputs, D0 and D1 are referenced by DV
CC
and DGND.
Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it can
be used to control other system components.
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input
clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1. Register values remain
unchanged.
Digital Ground Pin.
Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V.
Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V.
Ground Reference Point for Analog Circuitry.
Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V.
This pin is used in association with an optional external resistor to AGND to program the short-circuit current of
the output amplifiers. Refer to the Features section for further details.
Ground Reference Pin for DAC D Output Amplifier.
Analog Output Voltage of DAC D. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier
is capable of directly driving a 10 kΩ, 200 pF load.
2
SCLK
3
4
5
1
6
SDIN
SDO
CLR
1
LDAC
7, 8
D0, D1
9
RSTOUT
10
RSTIN
11
12
13, 31
14
15, 30
16
DGND
DV
CC
AV
DD
PGND
AV
SS
ISCC
17
18
AGNDD
VOUTD
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