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參數(shù)資料
| 型號： | AD5764CSUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT QUAD BIPO 32-TQFP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產品變化通告： | AD5764(R), AD5744R Product Change 04/Sept/2009 |
| 設計資源： | High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5764 (CN0006) |
| 標準包裝： | 500 |
| 設置時間： | 8µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 275 mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應商設備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，雙極 |
| 采樣率（每秒）： | 1.26M |
| 配用： | EVAL-AD5764EBZ-ND - BOARD EVAL FOR AD5764 |
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Data Sheet
AD5764
Rev. F | Page 21 of 28
FUNCTION REGISTER
The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine
the function addressed. The functions available via the function register are outlined in Table 11 and Table 12.
Table 11. Function Register Options
REG2
REG1
REG0
A2
A1
A0
DB15:DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
NOP, data = don’t care
0
1
Don’t care
Local ground
offset adjust
D1 direction
D1 value
D0 direction
D0 value
SDO disable
0
1
0
Clear, data = don’t care
0
1
0
1
Load, data = don’t care
Table 12. Explanation of Function Register Options
Option
Description
NOP
No operation instruction used in readback operations.
Local Ground Offset Adjust
Set by the user to enable the local ground offset adjust function. Cleared by the user to disable the local
ground offset adjust function (default). Refer to the Design Features section for further details.
D0/D1 Direction
Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). Refer
to the Design Features section for further details.
D0/D1 Value
I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1
pins when configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is
active as an input. When enabled as inputs, these bits are don’t cares during a write operation.
SDO Disable
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
Clear
Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in
binary mode.
Load
Addressing this function updates the data register and consequently the analog outputs.
DATA REGISTER
The data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC channel the data transfer
is to take place (see Table 10). The data bits are in Position DB15 to Position DB0, as shown in Table 13.
Table 13. Programming the Data Register Bit Map
REG2
REG1
REG0
A2
A1
A0
DB15:DB0
0
1
0
DAC address
16-bit DAC data
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 10). The coarse gain register is a 2-bit register and allows the user to select the output range of each
Table 14. Programming the Coarse Gain Register Bit Map
REG2
REG1
REG0
A2
A1
A0
DB15: DB2
DB1
DB0
0
1
DAC address
Don’t care
CG1
CG0
Table 15. Output Range Selection
Output Range
CG1
CG0
±10 V (Default)
0
±10.2564 V
0
1
±10.5263 V
1
0
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| AD5764RBSUZ | 功能描述:IC DAC 16BIT QUAD VOUT 32-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
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