參數(shù)資料
型號(hào)： AD5755ACPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 30/52頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT QUAD 64-LFCSP
視頻文件： AD5755: 16-Bit Multi-Channel, Voltage and Current Output DAC
特色產(chǎn)品： AD5755 / AD5755-1 / AD5757 DACs
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 11µs
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類(lèi)型： 4 電流，4 電壓
采樣率（每秒）： *
其它名稱(chēng)： AD5755ACPZ-REEL7DKR
AD5755
Data Sheet
Rev. C | Page 36 of 52
DAC Control Register
The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 20 and Table 21.
Table 20. Programming DAC Control Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
INT_ENABLE
CLR_EN
OUTEN
RSET
DC_DC
OVRNG
R2
R1
R0
1
X = don’t care.
Table 21. DAC Control Register Functions
Bit
Description
INT_ENABLE
Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel. Does not enable the output. Can
only be done on a per channel basis. It is recommended to set this bit and allow a >200 s delay before enabling the
output because this results in a reduced output enable glitch. See Figure 29 and Figure 47 for plots of this glitch.
CLR_EN
Per channel clear enable bit. Selects if this channel clears when the CLEAR pin is activated.
CLR_EN = 1, channel clears when the part is cleared.
CLR_EN = 0, channel does not clear when the part is cleared (default).
OUTEN
Enables/disables the selected output channel.
OUTEN = 1, enables channel.
OUTEN = 0, disables channel (default).
RSET
Selects an internal or external current sense resistor for the selected DAC channel.
RSET = 0, selects the external resistor (default).
RSET = 1, selects the internal resistor.
DC_DC
Powers the dc-to-dc converter on the selected channel.
DC_DC = 1, powers up the dc-to-dc converter.
DC_DC = 0, powers down the dc-to-dc converter (default).
This allows per channel dc-to-dc converter power-up/down. To power down the dc-to-dc converter, the OUTEN and
INT_ENABLE bits must also be set to 0.
All dc-to-dc converters can also be powered up simultaneously using the DCDC_All bit in the main control register.
OVRNG
Enables 20% overrange on voltage output channel only. No current output overrange available.
OVRNG = 1, enabled.
OVRNG = 0, disabled (default).
R2, R1, R0
Selects the output range to be enabled.
R2
R1
R0
Output Range Selected
0
0 V to 5 V voltage range (default).
0
1
0 V to 10 V voltage range.
0
1
0
±5 V voltage range.
0
1
±10 V voltage range.
1
0
4 mA to 20 mA current range.
1
0
1
0 mA to 20 mA current range.
1
0
0 mA to 24 mA current range.
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參數(shù)描述
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AD5757_11 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Quad Channel, 16-Bit,Serial Input, 4 mA to 20 mA Output DAC, Dynamic Power Control
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