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參數資料
| 型號： | AD5754BREZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 13/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT DSP/SRL 24TSSOP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 設計資源： | Software Configurable 16-Bit Quad-Channel Unipolar/Bipolar Voltage Output Using AD5754 (CN0086) |
| 標準包裝： | 1,000 |
| 設置時間： | 10µs |
| 位數： | 16 |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 4 |
| 電壓電源： | 模擬和數字，雙 ± |
| 功率耗散（最大）： | 310mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm）裸露焊盤 |
| 供應商設備封裝： | 24-TSSOP 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
| 輸出數目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 100k |
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AD5724/AD5734/AD5754
Rev. D | Page 20 of 32
LOAD DAC (LDAC)
After data has been transferred into the input register of the
DACs, there are two ways to update the DAC registers and DAC
outputs. Depending on the status of both SYNC and LDAC, one
of two update modes is selected: individual DAC updating or
simultaneous updating of all DACs.
SYNC
SCLK
VOUT
DAC
REGISTER
INTERFACE
LOGIC
OUTPUT
AMPLIFIER
LDAC
SDO
SDIN
REFIN
INPUT
REGISTER
12-/14-/16-BIT
DAC
06
46
8-
0
09
Figure 41. Simplified Diagram of Input Loading Circuitry for One DAC
Individual DAC Updating
In this mode, LDAC is held low while data is being clocked into
the input shift register. The addressed DAC output is updated
on the rising edge of SYNC.
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is being clocked
into the input shift register. All DAC outputs are asynchronously
updated by taking LDAC low after SYNC has been taken high.
The update now occurs on the falling edge of LDAC.
ASYNCHRONOUS CLEAR (CLR)
CLR is an active low clear that allows the outputs to be cleared
to either zero-scale code or midscale code. The clear code value is
user-selectable via the CLR select bit of the control register (see
the
section). It is necessary to maintain
CLR low
for a minimum amount of time to complete the operation (see
). When the
CLR signal is returned high, the output
remains at the cleared value until a new value is programmed.
The outputs cannot be updated with a new value while the CLR
pin is low. A clear operation can also be performed via the clear
command in the control register.
CONFIGURING THE AD5724/AD5734/AD5754
When the power supplies are applied to the AD5724/AD5734/
AD5754, the power-on reset circuit ensures that all registers
default to 0. This places all channels in power-down mode. The
DVCC should be brought high before any of the interface lines
are powered. If this is not done, the first write to the device may
be ignored. The first communication to the AD5724/AD5734/
AD5754 should be to set the required output range on all
channels (the default range is the 5 V unipolar range) by writing
to the output range select register. The user should then write to
the power control register to power on the required channels. To
program an output value on a channel, that channel must first
be powered up; any writes to a channel while it is in power-down
mode are ignored. The AD5724/ AD5734/AD5754 operate with a
wide power supply range. It is important that the power supply
applied to the parts provides adequate headroom to support the
chosen output ranges.
TRANSFER FUNCTION
to output voltage for the AD5754, AD5734, and AD5724, respec-
tively, for all output voltage ranges. For unipolar output ranges,
the data coding is straight binary. For bipolar output ranges, the
data coding is user-selectable via the BIN/2sCOMP pin and can
be either offset binary or twos complement.
For a unipolar output range, the output voltage expression is
given by
×
=
N
REFIN
OUT
D
Gain
V
2
For a bipolar output range, the output voltage expression is given by
2
REFIN
N
REFIN
OUT
V
Gain
D
Gain
V
×
×
=
where:
D
is the decimal equivalent of the code loaded to the DAC.
N
is the bit resolution of the DAC.
VREFIN
is the reference voltage applied at the REFIN pin.
Gain
is an internal gain whose value depends on the output
range selected by the user, as shown in Table 6.
Table 6. Internal Gain Values
Output Range (V)
Gain Value
+5
2
+10
4
+10.8
4.32
±5
4
±10
8
±10.8
8.64
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD5754R | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete, Quad, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DACs |
| AD5754RBREZ | 功能描述:IC DAC 16BIT DSP/SRL 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設置時間:4µs 位數:12 數據接口:串行 轉換器數目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-uMAX 包裝:管件 輸出數目和類型:2 電壓，單極 采樣率（每秒）:* 產品目錄頁面:1398 (CN2011-ZH PDF) |
| AD5754RBREZ-REEL7 | 功能描述:IC DAC 16BIT DSP/SRL 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 產品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數:16 數據接口:并聯(lián) 轉換器數目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD5755 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA |
| AD5755_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad Channel, 16-Bit, Serial Input, 4 mA to 20 mA and Voltage Output DAC, Dynamic Power Control |
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