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參數(shù)資料
| 型號(hào)： | AD573JP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/10頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT SAR REGISTER 20PLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 50k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 20-PLCC（9x9） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極；1 個(gè)單端，雙極 |
AD573
–8–
It is also possible to write a faster-executing assembly-language
routine to control the AD573. Such a routine will require a de-
lay between starting and reading the converter. This can be eas-
ily implemented by calling the Apple’s WAIT subroutine (which
resides at location $FCA8) after loading the accumulator with a
number greater than or equal to two.
8085-Series Microprocessor Interface
The AD573 can also be used with 8085-series microprocessors.
These processors use separate control signals for RD and WR,
as opposed to the single R/W control signal used in the 6800/
6500 series processors.
There are two constraints related to operation of the AD573
with 8085-series processors. The first problem is the width of
the CONVERT pulse. The circuit shown in Figure 17 (essen-
tially the same as that shown in Figure 13) will produce a wide
enough CONVERT pulse when the 8085 is running at 5 MHz.
For 8085 systems running at slower clock rates (3 MHz), the
flip-flop-based circuit can be eliminated since the WR pulse will
be approximately 500 ns wide.
The other consideration is the access time of the AD573’s three-
state output data buffers, which is 250 ns maximum. It may be
necessary to insert wait states during RD operations from the
AD573. This will not be a problem in systems using memories
with comparable access times, since wait states will have already
been provided in the basic system design.
Figure 17. AD573–8085A Interface Connections
The following assembly-language subroutine can be used to
control an AD573 residing at memory locations 3000H and
3001H. The 10 bits of data are returned (left-justified) in the
DE register pair.
ADC:
LXI H, 3000 ; LOAD HL WITH AD573 ADDRESS
MOV M, A
; START CONVERSION
MVI B, 06
; LOAD DELAY PERIOD
LOOP: DCR B
; DELAY LOOP
JNZ LOOP
;
MOV A, M
; READ LOW BYTE
ANI C0
; MASK LOWER 6 BITS
MOV E, A
; STORE CLEAN LOW BYTE IN E
INR L
; LOAD HIGH BYTE ADDRESS
MOV D, M
; MOVE HIGH BYTE TO D
RET
; EXIT
REV. B
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參數(shù)描述 |
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| AD573JPZ | 功能描述:IC ADC 10BIT SAR REGISTER 20PLCC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD573KD | 功能描述:IC ADC 10BIT SAR REG 20-CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| AD573KD/+ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD573KN | 制造商:Analog Devices 功能描述:ADC Single SAR 10-bit Parallel 20-Pin PDIP N 制造商:Rochester Electronics LLC 功能描述:IC, MONO 10-BIT A/D CONV - Bulk |
| AD573KN/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 10-Bit |
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