參數資料
| 型號： | AD568KQ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 10/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT HS MONO 35NS 24CDIP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 設置時間： | 35ns |
| 位數： | 12 |
| 數據接口： | 并聯 |
| 轉換器數目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-CDIP（0.300"，7.62mm） |
| 供應商設備封裝： | 24-CDIP |
| 包裝： | 管件 |
| 輸出數目和類型： | 1 電流，單極；1 電流，雙極；1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
AD568
REV. A
–5–
13
16
15
14
24
23
22
21
20
19
18
17
12
11
10
9
8
1
2
3
4
7
6
5
AD568
+15V
REFCOM
–15V
IBPO
RL
ACOM
LCOM
SPAN
THCOM
VTH
IOUT
DIGITAL
INPUTS
0.2F
0.1F
–15V
+15V
ANALOG
GND PLANE
DIGITAL
GND PLANE
DIGITAL
SUPPLY
GROUND
100pF
RTH
1k
+5V
NC
ANALOG
OUTPUT
ANALOG
SUPPLY
GROUND
Figure 5. Bipolar Output Unbuffered
±1.024 V
Optional Gan and Zero Adjustment
The gain and offset are laser trimmed to minimize their effects
on circuit performance. However, in some applications, it may
be desirable to externally reduce these errors further. In those
cases, the following procedures are suggested.
UNIPOLAR MODE: (Refer to Figure 6)
Step 1 – Set all bits (BIT 1–BIT 12) to Logic “0” (OFF)—note
the output voltage. This is the offset error.
Step 2 – Set all bits to Logic “1” (ON). Adjust the gain trim re-
sistor so that the output voltage is equal to the desired full scale
minus 1 LSB plus the offset error measured in step 1.
Step 3 – Reset all bits to Logic “0” (OFF). Adjust the offset
trim resistor for 0 V output.
13
16
15
14
24
23
22
21
20
19
18
17
12
11
10
9
8
1
2
3
4
7
6
5
IBPO
RL
ACOM
LCOM
IOUT
DIGITAL
INPUTS
5.11k
BIT 1
MSB
BIT 12
LSB
ANALOG
OUTPUT
(0 TO 1.024V)
100
OFFSET
GAIN
20
Figure 6. Unbuffered Unipolar Gain and Zero Adjust
BIPOLAR MODE (Refer to Figure 7)
Step 1 – Set bits to offset binary “zero” (10 . . . 00). Adjust the
zero resistor to produce 0 V at the DAC output. This removes
the bipolar zero error.
Step 2 – Set all bits to Logic “1” (ON). Adjust gain trim resistor
so the output voltage is equal to the desired full-scale minus
l LSB .
Step 3 – (Optional) If precise trimming of the bipolar offset is
preferred to trimming of bipolar zero: set all bits to Logic “0”
(OFF). Trim the zero resistor to produce the desired negative
full scale at the DAC output. Note: this may slightly compro-
mise the bipolar zero trim.
13
16
15
14
24
23
22
21
20
19
18
17
12
11
10
9
8
1
2
3
4
7
6
5
AD568
IBPO
RL
ACOM
LCOM
IOUT
DIGITAL
INPUTS
5.11k
BIT 1
MSB
BIT 12
LSB
ANALOG
OUTPUT
(–0.512 TO
0.512V)
75
GAIN
20
20k
VEE
VCC
ZERO
Figure 7. Bipolar Unbuffered Gain and Zero Adjust
BUFFERED VOLTAGE OUTPUT
For full-scale outputs of greater than 1 V, some type of external
buffer amplifier is required. The AD840 fills this requirement
perfectly, settling to 0.025% from a 10 V full-scale step in less
than 100 ns.
A 1 k
span resistor has been provided on chip for use as a
feedback resistor in buffered applications. Using RSPAN (Pins 15,
16) introduces a 100 mW code-dependent power source onto
the chip which may generate a slight degradation in linearity.
Maximum linearity performance can be realized by using an ex-
ternal span resistor.
13
16
15
14
24
23
22
21
20
19
18
17
12
11
10
9
8
1
2
3
4
7
6
5
AD568
+15V
REFCOM
–15V
IBPO
RL
ACOM
LCOM
SPAN
THCOM
VTH
IOUT
DIGITAL
INPUTS
0.2F
0.1F
–15V
+15V
ANALOG
GND PLANE
DIGITAL
GND PLANE
DIGITAL
SUPPLY
GROUND
100pF
+5V
ANALOG
OUTPUT
ANALOG
SUPPLY
GROUND
5pF
–VS
+VS
100
RTH
1k
AD840
AMPLIFIER NOISE GAIN: 11
Figure 8. Unipolar Output Buffered 0 to –10.24V
Unipolar Inverting Configuration
Figure 8 shows the connections for producing a – 10.24 V full-
scale swing. This configuration uses the AD568 in the current
output mode into a summing junction at the inverting input ter-
minal of the external op amp. With the load resistor RL
grounded, the DAC has an output impedance of 100
. This
produces a noise gain of 11 from the noninverting terminal of
the op amp, and hence, satisfies the stability criterion of the
AD840 (stable at a gain of 10). The addition of a 5 pF compen-
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