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參數(shù)資料
| 型號： | AD5641BKS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.7 V to 5.5 V, <100 uA, 14-Bit nanoDAC D/A in SC70 Package |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PDSO6 |
| 封裝： | PLASTIC, SC-70, MO-203AB, SURFACE MOUNT PACKAGE-6 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 572K |
| 代理商： | AD5641BKS |
Preliminary Technical Data
AD5641
Rev. PrC | Page 13 of 20
0
DIN
DB15
DB16
DB0
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 16
TH
FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16
TH
FALLING EDGE
SYNC
SCLK
Figure 27. SYNC Interrupt Facility
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 16 falling edges of SCLK and the DAC is updated on the
16
th
falling edge. However, if SYNC is brought high before the
16
th
falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 27).
POWER-ON RESET
The AD5641 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
zeros and the output voltage is 0 V. It remains there until a valid
write sequence is made to the DAC. This is useful in applica-
tions in which it is important to know the state of the DAC’s
output while it is in the process of powering up.
POWER-DOWN MODES
The AD5641 have four separate modes of operation. These
modes are software-programmable by setting two bits (DB15
and DB14) in the control register. Table 6 shows how the state of
the bits corresponds to the mode of operation of the device.
Table 6. Modes of Operation for the AD5641
DB15
DB14
0
0
0
1
1
0
1
1
Operating Mode
Normal operation
Power-down mode
1 k to GND
100 k to GND
Three-state
When both bits are set to 0, the part works normally with its
normal power consumption of 100 μA maximum at 5 V.
However, for the three power-down modes, the supply current
falls to <100 nA at 3 V. Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options: the output is connected internally to GND through a
1 k resistor or a 100 k resistor, or the output is left open-
circuited (three-state). Figure 28 shows the output stage.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
V
OUT
RESISTOR
STRING DAC
AMPLIFIER
0
Figure 28. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are all shut down when the power-
down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
power-down is typically 2.5 μs for V
DD
= 5 V and 5 μs for
V
DD
= 3 V. See Figure 20 for a plot.
MICROPROCESSOR INTERFACING
AD5641 to ADSP-2101/ADSP-2103 Interface
Figure 29 shows a serial interface between the AD5641 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in SPORT transmit alternate framing mode.
The ADSP-2101/ADSP-2103 SPORT is programmed through
the SPORT control register and should be configured as follows:
internal clock operation, active low framing, and 16-bit word
length. Transmission is initiated by writing a word to the Tx
register after the SPORT has been enabled.
ADSP-2101/
ADSP-2103*
AD5641*
*ADDITIONAL PINS OMITTED FOR CLAIRTY
TFS
DT
SCLK
SYNC
DIN
SCLK
0
Figure 29. AD5641 to ADSP-2101/ADSP-2103 Interface
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