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參數(shù)資料
| 型號： | AD5626BRMZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC NANO 12BIT 8-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | nanoDAC™ |
| 設(shè)置時(shí)間： | 16µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 12.5mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
| 其它名稱： | AD5626BRMZ-REEL7DKR |
AD5626
Rev. A | Page 16 of 20
MICROPROCESSOR INTERFACING
AD5626 to MC68HC11 Interface
The circuit illustrated in Figure 35 shows a serial interface
between the AD5626 and the MC68HC11 8-bit microcontroller.
SCK of the MC68HC11 drives SCLK of the AD5626, whereas
the MOSI output drives the serial data line, SDIN, of the AD5626.
The CLR, LDAC, and CS signals of the DAC are derived from
the PC1, PD5, and PC0 port lines, respectively, as shown.
For correct operation of the serial interface, configure the
MC68HC11 such that its CPOL bit is set to 1 and its CPHA bit
is also set to 1. When the serial data is to be transmitted to the
DAC, PC0 is taken low, asserting the CS input of the DAC. When
the MC68HC11 is configured in this manner, serial data on
MOSI is valid on the rising edge of SCLK. The MC68HC11
transmits its serial data in 8-bit bytes (MSB first), with only
eight rising clock edges occurring in the transmit cycle. To load
data to the input serial register of the AD5626, PC0 is left low
after the first eight bits are transferred, and a second byte of
data is then transferred serially to the AD5626. During the
second byte load, the first 4 MSBs of the first byte are pushed
out of the input shift register of the DAC. At the end of the
second byte load, PC0 is taken high. To prevent accidental
advancing of the internal shift register, SCLK must already be
asserted before PC0 is taken high. To transfer the contents of
the input shift register to the DAC register, PD5 is taken low,
asserting the LDAC input. The CLR input of the DAC, controlled
by the MC68HC11 PC1 port, provides an asynchronous clear
function, setting the DAC output to zero.
06
75
7-
0
35
*ADDITIONAL PINS OMITTED FOR CLARITY.
PC1
PC0
PD5
SCK
MOSI
MC68HC11*
AD5626
CLR
CS
LDAC
SCLK
SDIN
Figure 35. AD5626 to MC68HC11 Interface
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