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參數(shù)資料
| 型號(hào)： | AD5621AKSZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 5V MICROPWR SC70-6 |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | nanoDAC™ |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 500µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-TSSOP，SC-88，SOT-363 |
| 供應(yīng)商設(shè)備封裝： | SC-70-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 產(chǎn)品目錄頁面： | 783 (CN2011-ZH PDF) |
| 其它名稱： | AD5621AKSZ-REEL7DKR |
Data Sheet
AD5601/AD5611/AD5621
Rev. G | Page 17 of 24
AD5601/AD5611/AD5621 to Blackfin ADSP-BF53x
Interface
Figure 48 shows a serial interface between the AD5601/AD5611/
AD5621 and the Blackfin ADSP-BF53x microprocessor. The
ADSP-BF53x processor family incorporates two dual-channel
synchronous serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5601/AD5611/AD5621, the setup for the interface is as
follows: DT0PRI drives the SDIN pin of the AD5601/AD5611/
AD5621, while TSCLK0 drives the SCLK of the part. The SYNC
is driven from TFS0.
Figure 48. AD5601/AD5611/AD5621 to Blackfin ADSP-BF53x Interface
AD5601/AD5611/AD5621 to 80C51/80L51 Interface
Figure 49 shows a serial interface between the AD5601/
AD5611/AD5621 and the 80C51/80L51 microcontroller. The
setup for the interface is as follows: TxD of the 80C51/80L51
drives SCLK of the AD5601/AD5611/AD5621, while RxD
drives the serial data line of the part. The SYNC signal is again
derived from a bit programmable pin on the port. In this case,
Port Line P3.3 is used. When data is to be transmitted to the
AD5601/AD5611/AD5621, P3.3 is taken low. The 80C51/80L51
transmit data only in 8-bit bytes; therefore, only eight falling
clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted,
and a second write cycle is initiated to transmit the second byte
of data. P3.3 is taken high following the completion of this
cycle. The 80C51/80L51 output the serial data LSB first. The
AD5601/AD5611/AD5621 require data with the MSB as the
first bit received. The 80C51/80L51 transmit routine should
take this into account.
Figure 49. AD5601/AD5611/AD5621 to 80C51/80L51 Interface
AD5601/AD5611/AD5621 to MICROWIRE Interface
Figure 50 shows an interface between the AD5601/AD5611/
AD5621 and any MICROWIRE-compatible device. Serial data
is shifted out on the falling edge of the serial clock and is
clocked into the AD5601/AD5611/AD5621 on the rising edge
of the SK.
Figure 50. AD5601/AD5611/AD5621 to MICROWIRE Interface
ADSP-BF53x*
AD5601/AD5611/
AD5621*
*ADDITIONAL PINS OMITTED FOR CLARITY
DT0PRI
TSCLK0
TFS0
SDIN
SCLK
SYNC
06853-
047
80C51/80L51*
AD5601/AD5611/
AD5621*
*ADDITIONAL PINS OMITTED FOR CLARITY
P3.3
TxD
RxD
SYNC
SCLK
SDIN
06853-
048
MICROWIRE*
AD5601/AD5611/
AD5621*
*ADDITIONAL PINS OMITTED FOR CLARITY
CS
SK
SO
SYNC
SCLK
SDIN
06853-
049
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