參數(shù)資料
型號(hào)： AD5557CRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/20頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT 2CH I OUT 38TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源： Precision, Unipolar, Inverting Conversion Using AD5547/57 DAC (CN0026)
Precision, Unipolar, Noninverting Configuration for the AD5547/57 DAC (CN0027)
Precision, Bipolar, Configuration for AD5547/AD5557 DAC (CN0028)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 500ns
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 55µW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 38-TFSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 38-TSSOP
包裝： 管件
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 2M
產(chǎn)品目錄頁(yè)面： 783 (CN2011-ZH PDF)
AD5547/AD5557
Data Sheet
Rev. D | Page 4 of 20
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
SUPPLY CHARACTERISTICS
Power Supply Range
VDD RANGE
2.7
5.5
V
Positive Supply Current
IDD
Logic inputs = 0 V
10
μA
Power Dissipation
PDISS
Logic inputs = 0 V
0.055
mW
Power Supply Sensitivity
PSS
VDD = ±5%
0.003
%/%
AC CHARACTERISTICS4
Output Voltage Settling Time
tS
To ±0.1% of full scale, data cycles from zero scale
to full scale to zero scale
0.5
μs
Reference Multiplying BW
BW
VREF = 100 mV rms, data = full scale
6.8
MHz
DAC Glitch Impulse
Q
VREF = 0 V, midscale – 1 to midscale
3.5
nV-s
Multiplying Feedthrough Error
VOUT/VREF
VREF = 100 mV rms, f = 10 kHz
78
dB
Digital Feedthrough
QD
WR = 1, LDAC toggles at 1 MHz
7
nV-s
Total Harmonic Distortion
THD
VREF = 5 V p-p, data = full scale, f = 1 kHz
104
dB
Output Noise Density
eN
f = 1 kHz, BW = 1 Hz
12
nV/√Hz
Analog Crosstalk
CAT
Signal input at Channel A and measures the
output at Channel B, f = 1 kHz
95
dB
1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP97 I-to-V converter amplifier. The device RFB terminal is
tied to the amplifier output. The +IN pin of the OP97 is grounded, and the IOUT of the DAC is tied to the OP97’s IN pin. Typical values represent average readings
measured at 25°C.
2 Guaranteed by design; not subject to production testing.
3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and are timed from a voltage level of 1.5 V.
4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where the AD8065 was used.
Timing Diagram
04
45
2-
0
18
tWR
tDS
tDH
tLWD
tLDAC
tRS
WR
DATA
LDAC
RS
Figure 3. AD5547/AD5557 Timing Diagram
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