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參數(shù)資料
| 型號： | AD5555CRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT DUAL SRL IN 16TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 500ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 55µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 2M |
| 產(chǎn)品目錄頁面： | 783 (CN2011-ZH PDF) |
Data Sheet
AD5545/AD5555
Rev. G | Page 15 of 24
REFERENCE SELECTION
When selecting a reference for use with the AD55xx series
of current output DACs, pay attention to the output voltage,
temperature coefficient specification of the reference. Choosing
a precision reference with a low output temperature coefficient
minimizes error sources. Table 10 lists some of the references
available from Analog Devices, Inc., that are suitable for use
with this range of current output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code-dependent output resistance of the DAC,
the input offset voltage of an op amp is multiplied by the variable
gain of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed upon the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, can cause the DAC to be
nonmonotonic.
The input bias current of an op amp also generates an offset at
the voltage output because of the bias current flowing in the
feedback resistor, RFB.
Common-mode rejection of the op amp is important in voltage-
switching circuits because it produces a code-dependent error
at the voltage output of the circuit.
Provided that the DAC switches are driven from true wideband
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage-switching
DAC circuit is determined largely by the output op amp. To obtain
minimum settling time in this configuration, minimize capacitance
at the VREF node (the voltage output node in this application) of
the DAC. This is done by using low input capacitance buffer
amplifiers and careful board design.
Analog Devices offers a wide range of amplifiers for both precision
dc and ac applications, as listed in Table 11 and Table 12.
Table 10. Suitable Analog Devices Precision References
Part No.
Output Voltage (V)
Initial Tolerance (%)
Maximum Temperature
Drift (ppm/°C)
ISS (mA)
Output Noise (V p-p)
Package(s)
10
0.05
3
1
20
SOIC-8
10
0.05
9
1
20
TSOT-5, SC70-5
5.0
0.06
3
1
10
SOIC-8
5.0
0.06
9
1
10
TSOT-5, SC70-5
2.5
0.1
3
1
6
SOIC-8
2.5
0.1
9
1
6
TSOT-5, SC70-5
3.0
0.1
3
1
10
SOIC-8
3.0
0.1
9
1
10
TSOT-5, SC70-5
2.048
0.05
3
0.5
1.75
SOIC-8, MSOP-8
2.50
0.04
3
0.5
1.75
SOIC-8, MSOP-8
3.00
0.04
3
0.5
2
SOIC-8, MSOP-8
5.00
0.04
3
0.5
3.4
SOIC-8, MSOP-8
2.500
0.04
3
0.8
3.5
SOIC-8, MSOP-8
5.000
0.04
3
0.8
8
SOIC-8, MSOP-8
2.5
0.16
9
0.12
5
TSOT-5
5.0
0.10
9
0.12
8
TSOT-5
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