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參數(shù)資料
| 型號： | AD5541ABRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 2.7-5.5V 10-MSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 系列： | nanoDAC™ |
| 設(shè)置時(shí)間： | 1µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 825µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | * |
| 采樣率（每秒）： | 1M |
AD5541A
Rev. A | Page 15 of 20
UNIPOLAR OUTPUT OPERATION
This DAC is capable of driving unbuffered loads of 60 kΩ.
Unbuffered operation results in low supply current, typically
300 μA, and a low offset error. The AD5541A provides a
unipolar output swing ranging from 0 V to VREF 1 LSB.
Figure 31 shows a typical unipolar output voltage circuit. The
code table for this mode of operation is shown in Table 8. The
low offset and zero-drift reference buffer.
Table 8. Unipolar Code Table
DAC Latch Contents
MSB
LSB
Analog Output
1111 1111 1111 1111
VREF × (65,535/65,536)
1000 0000 0000 0000
VREF × (32,768/65,536) = VREF
0000 0000 0000 0001
VREF × (1/65,536)
0000 0000 0000 0000
0 V
Assuming a perfect reference, the unipolar worst-case output
voltage can be calculated from the following equation:
()
INL
V
D
V
ZSE
GE
REF
UNI
OUT
+
×
=
16
2
where:
VOUTUNI is the unipolar mode worst-case output.
D is the code loaded to DAC.
VREF is the reference voltage applied to the part.
VGE is the gain error in volts.
VZSE is the zero-scale error in volts.
INL is the integral nonlinearity in volts.
OUTPUT AMPLIFIER SELECTION
For bipolar mode, a precision amplifier should be used and
supplied from a dual power supply. This provides the ±VREF
output. In a single-supply application, selection of a suitable
op amp may be more difficult because the output swing of the
amplifier does not usually include the negative rail, in this case,
AGND. This can result in some degradation of the specified
performance unless the application does not use codes near zero.
The selected op amp must have a very low offset voltage (the
DAC LSB is 38 μV with a 2.5 V reference) to eliminate the need
for output offset trims. Input bias current should also be very
low because the bias current, multiplied by the DAC output
impedance (approximately 6 kΩ), adds to the zero-code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code independent, but to minimize gain errors,
the input impedance of the output amplifier should be as high
as possible. The amplifier should also have a 3 dB bandwidth of
1 MHz or greater. The amplifier adds another time constant to
the system, thus increasing the settling time of the output. A
higher 3 dB amplifier bandwidth results in a shorter effective
settling time of the combined DAC and amplifier.
08
51
6-
02
3
VOUT
VIN
REF
DGND
AGND
VDD
DIN
SCLK
CS
AD5541A
AD820/
OP196
AD8628
ADR421
+
0.1F
10F
UNIPOLAR
OUTPUT
EXTERNAL
OP AMP
5V
SERIAL
INTERFACE
1F
6
2
4
Figure 31. Unipolar Output
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