Limit at TMIN
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EVAL-AD5532EBZ-ND - BOARD EVAL FOR AD5532
AD5532
Rev. D | Page 6 of 20
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Table 3.
Limit at TMIN, TMAX (A Version)
Unit
Conditions/Comments
t1
0
ns min
CS to WR setup time
t2
0
ns min
CS to WR hold time
t3
50
ns min
CS pulse width low
t4
50
ns min
WR pulse width low
t5
20
ns min
A4鈥揂0, CAL, OFFS_SEL to WR setup time
t6
7
ns min
A4鈥揂0, CAL, OFFS_SEL to WR hold time
1 See Figure 2 and Figure 3, the parallel interface timing diagrams.
2
PARALLEL INTERFACE TIMING DIAGRAMS
Guaranteed by design and characterization, not production tested.
00939-C-002
A4鈥揂0, CAL,
OFFS_SEL
t1
t3
t2
t4
t5
t6
CS
WR
Figure 2. Parallel Write (ISHA Mode Only)
00939-C-003
200
渭AI
OL
200
渭AI
OH
1.6V
TO OUTPUT
PIN
CL
50pF
Figure 3. Load Circuit for DOUT Timing Specifications
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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AD5532ABCZ-1 鍔熻兘鎻忚堪:IC DAC 14BIT VOUT 32CH 74-CSPBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 瑷�(sh猫)缃檪(sh铆)闁�:4.5µs 浣嶆暩(sh霉):12 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶锛孲PI? 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:鍠浕婧� 鍔熺巼鑰楁暎锛堟渶澶э級:- 宸ヤ綔婧害:-40°C ~ 125°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-SOIC锛�0.154"锛�3.90mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-SOICN 鍖呰:鍓垏甯� (CT) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤碉紱1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:* 鍏跺畠鍚嶇ū:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND
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