參數資料
型號: AD5530BRUZ
廠商: Analog Devices Inc
文件頁數: 4/20頁
文件大?。?/td> 0K
描述: IC DAC 12BIT SRL IN/VOUT 16TSSOP
產品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 96
設置時間: 20µs
位數: 12
數據接口: 串行
轉換器數目: 1
電壓電源: 模擬和數字
功率耗散(最大): 60mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 16-TSSOP
包裝: 管件
輸出數目和類型: 1 電壓,雙極
采樣率(每秒): 50k
產品目錄頁面: 782 (CN2011-ZH PDF)
AD5530/AD5531
Rev. B | Page 12 of 20
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity.
Zero-Scale Error
Zero-scale error is a measure of the output error when all 0s are
loaded to the DAC latch.
Full-Scale Error
This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s loaded
into the DAC latch, should be 2 VREF 1 LSB.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range. It is
the deviation in slope of the DAC transfer characteristic from ideal.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is specified as the area of the glitch in nV-s and is
measured when the digital input code is changed by 1 LSB at
the major carry transition.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and is measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice versa.
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