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參數(shù)資料
| 型號： | AD5504BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT SPI 16-TSSOP |
| 產(chǎn)品培訓模塊： | DAC Architectures |
| 設(shè)計資源： | Powering a 30V DAC from a 3V supply (CN0193) |
| 標準包裝： | 1 |
| 設(shè)置時間： | 45µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | * |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | * |
Data Sheet
AD5504
Rev. B | Page 9 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
SYNC
SCLK
SDI
AGND
DGND
SDO
CLR
LDAC
16
15
14
13
12
11
10
9
ALARM
VDD
R_SEL
VOUTC
VOUTD
VOUTB
VOUTA
VLOGIC
TOP VIEW
(Not to Scale)
AD5504
07994-
005
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the input register and the DAC register are set to 0x000 and the outputs to zero scale.
2
SYNC
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes
low, it enables the input shift register and data is transferred in on the rising edges of the following clocks. The
selected DAC register is updated on the 16th falling SCLK, unless SYNC is taken high before this edge, in which case, the
rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
3
SCLK
Serial Clock Input. Data is clocked into the input shift register on the rising edge of the serial clock input. Data can
be transferred at rates up to 16 MHz.
4
SDI
Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the rising edge of the
serial clock input.
5
SDO
Serial Data Output. CMOS output. This pin serves as the readback function for all DAC and control registers. Data
is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
6
DGND
Digital Ground Pin.
7
AGND
Analog Ground Pin.
8
LDAC
Load DAC Input. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new
data. This allows all DAC outputs to update simultaneously. Alternatively, this pin can be tied permanently low.
9
VOUTD
Buffered Analog Output Voltage from DAC D.
10
VOUTC
Buffered Analog Output Voltage from DAC C.
11
VOUTB
Buffered Analog Output Voltage from DAC B.
12
VOUTA
Buffered Analog Output Voltage from DAC A.
13
R_SEL
Range Select Pin. Tying this pin to DGND selects a DAC output range of 0 V to 60 V, alternatively tying R_SEL to
VLOGIC selects a DAC output range of 0 V to 30 V.
14
VDD
Positive Analog Power Supply. 10 V to 62 V for the specified performance. This pin should be decoupled with 0.1 F
ceramic capacitors and 10 F capacitors.
15
ALARM
Active Low CMOS Output Pin. This pin flags an alarm if the temperature on the die exceeds 110°C.
16
VLOGIC
Logic Power Supply; 2.3 V to 5.5 V. Decouple this pin with 0.1F ceramic capacitors and 10 F capacitors.
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