參數(shù)資料
型號(hào)： AD5453YUJZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/28頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT MULT 50MHZ TSOT23-8
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源： Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052)
Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053)
AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054)
Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055)
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-8 薄型，TSOT-23-8
供應(yīng)商設(shè)備封裝： TSOT-23-8
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型： 1 電流，單極；1 電流，雙極
采樣率（每秒）： 2.7M
產(chǎn)品目錄頁(yè)面： 782 (CN2011-ZH PDF)
其它名稱： AD5453YUJZ-REEL7DKR
Data Sheet
AD5450/AD5451/AD5452/AD5453
Rev. G | Page 7 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04587-003
AD5450/
AD5451/
AD5452/
AD5453
RFB 1
VREF 2
VDD 3
SYNC
4
IOUT1
GND
SCLK
SDIN
8
7
6
5
Figure 3. 8-Lead TSOT Pin Configuration
04587-004
AD5452/
AD5453
IOUT1 1
GND
2
SCLK
3
SDIN
4
RFB
VREF
VDD
SYNC
8
7
6
5
Figure 4. 8-Lead MSOP Pin Configuration
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.
TOP VIEW
(Not to Scale)
AD5453
3
SCLK
4
SDIN
1
IOUT1
2
GND
6 VDD
5 SYNC
8 RFB
7 VREF
04587-
205
Figure 5. 8-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No1
TSOT
MSOP
LFCSP
Mnemonic
Description
1
8
RFB
DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external
amplifier output.
2
7
VREF
DAC Reference Voltage Input.
3
6
VDD
Positive Power Supply Input. These parts can operate from a supply of 2.5 V to 5.5 V.
4
5
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. Data is
loaded to the shift register upon the active edge of the following clocks.
5
4
SDIN
Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial
clock input. By default, in power-up mode data is clocked into the shift register upon the falling
edge of SCLK. The control bits allow the user to change the active edge to a rising edge.
6
3
SCLK
Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge
of the serial clock input. Alternatively, by means of the serial control bits, the device can be
configured such that data is clocked into the shift register upon the rising edge of SCLK.
7
2
GND
Ground Pin.
8
1
IOUT1
DAC Current Output.
N/A
EPAD
Exposed pad must be connected to ground.
1
N/A = not applicable.
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