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參數(shù)資料
| 型號(hào)： | AD5444YRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 16/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT SERIAL OUT 10MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時(shí)間： | 16ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 50.5µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 2.7M |
| 產(chǎn)品目錄頁(yè)面： | 782 (CN2011-ZH PDF) |
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AD5444/AD5446
Data Sheet
Rev. E | Page 22 of 28
80C51/80L51 to AD5444/AD5446 Interface
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 50. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, while RxD drives the serial data line,
SDIN. P1.1 is a bit-programmable pin on the serial port and
is used to drive SYNC. When data is to be transmitted to the
switch, P1.1 is taken low. The 80C51/80L51 transmits data only
in 8-bit bytes; therefore, only eight falling clock edges occur in
the transmit cycle. To load data correctly to the DAC, P1.1 is
left low after the first eight bits are transmitted, and a second
write cycle is initiated to transmit the second byte of data.
Data on RxD is clocked out of the microcontroller on the rising
edge of TxD and is valid on the falling edge. As a result, no glue
logic is required between the DAC and microcontroller inter-
face. P1.1 is taken high following the completion of this cycle.
The 80C51/80L51 provides the LSB of its SBUF register as the
first bit in the data stream. The DAC input register requires its
data with the MSB as the first bit received. The transmit routine
should take this into account.
SCLK
TxD
8051*
SYNC
P1.1
SDIN
RxD
*ADDITIONAL PINS OMITTED FOR CLARITY
04588-
041
AD5444/AD5446*
Figure 50. 80C51/80L51 to AD5444/AD5446 Interface
MC68HC11 Interface to AD5444/AD5446 Interface
Figure 51 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and the clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR); see the 68HC11 User Manual. SCK
of the 68HC11 drives the SCLK of the DAC interface, the MOSI
output drives the serial data line (SDIN) of the AD5444/AD5446.
The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5444/AD5446, the SYNC line is
taken low (PC7). Data appearing on the MOSI output is valid
on the falling edge of SCK. Serial data from the 68HC11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
To load data to the DAC, PC7 is left low after the first eight bits
are transferred, and a second serial write operation is performed
to the DAC. PC7 is taken high at the end of this procedure.
SCLK
SCK
AD5444/AD5446*
SYNC
PC7
SDIN
MOSI
MC68HC11*
*ADDITIONAL PINS OMITTED FOR CLARITY
04588-
042
Figure 51. MC68HC11 to AD5444/AD5446 Interface
If the user wants to verify the data previously written to the
input shift register, the SDO line can be connected to MISO of
the MC68HC11, and, with SYNC low, the shift register clocks
data out on the rising edges of SCLK.
MICROWIRE to AD5444/AD5446 Interface
Figure 52 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register on the rising edge of SK, which
corresponds to the falling edge of the DAC SCLK.
SCLK
SK
MICROWIRE*
SYNC
CS
SDIN
SO
*ADDITIONAL PINS OMITTED FOR CLARITY
04588-
043
AD5444/AD5446*
Figure 52. MICROWIRE to AD5444/AD5446 Interface
PIC16C6x/7x to AD5444/AD5446 Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON); see the PIC16/17 Microcontroller User Manual.
In this example, I/O port RA1 is used to provide a SYNC
signal and enable the serial port of the DAC. This micro-
controller transfers only eight bits of data during each serial
transfer operation; therefore, two consecutive write operations
are required. Figure 53 shows the connection diagram.
SCLK
SCK/RC3
PIC16C6x/7x*
SYNC
RA1
SDIN
SDI/RC4
*ADDITIONAL PINS OMITTED FOR CLARITY
04588-
044
AD5444/AD5446*
Figure 53. PIC16C6x/7x to AD5444/AD5446 Interface
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| AD5444YRMZ-REEL | 功能描述:IC DAC 12BIT MULTIPLYING 10-MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標(biāo)準(zhǔn)包裝:91 系列:- 設(shè)置時(shí)間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5444YRMZ-REEL7 | 功能描述:IC DAC 12BIT MULTIPLYING 10-MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標(biāo)準(zhǔn)包裝:91 系列:- 設(shè)置時(shí)間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5445 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface |
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