All input control signals are specified with tR
參數(shù)資料
型號: AD5441BRMZ
廠商: Analog Devices Inc
文件頁數(shù): 13/17頁
文件大?。?/td> 0K
描述: IC DAC 12BIT SERIAL IN 8MSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 50
設(shè)置時間: 500ns
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 55µW
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極
采樣率(每秒): *
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
配用: EVAL-AD5541/42EBZ-ND - BOARD EVAL FOR AD5441/2
AD5441
Rev. A | Page 4 of 16
TIMING CHARACTERISTICS
All input control signals are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD + 2.5 V
to 5.5 V, VREF = 10 V; temperature range = 40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted.
Table 2. Timing Characteristics
Parameter
2.5 V
5.5 V
Unit
Conditions/Comments
tDS
10
5
ns min
Data setup
tDH
5
ns min
Data hold
tCH
15
10
ns min
Clock width high
tCL
15
10
ns min
Clock width low
tLD
20
10
ns min
Load pulse width
tLD1
0
ns min
LD DAC high to MSB CLK high
tASB
0
ns min
LSB CLK to LD DAC
Timing Diagrams
SRI
CLK
LD
D11
D10
D9
D8
D6D5
D4D3D2D1
D0
D7
tLD1
tASB
DAC REGISTER LOAD
0
64
92
-1
02
Figure 2. Full Data Transmission
SRI
CLK
tDS
tDH
tCL
tCH
Dxx
DATA LOADED MSB(D11) FIRST
0
64
92
-1
03
Figure 3. Bit Data Transmission
FS
ZS
VOUT
tLD
±1LSB
ERROR BAND
LD
06
49
2-
1
0
4
Figure 4. Output Transition
Table 3. Control Logic Truth Table
CLK
LD
Serial Shift Register Function
DAC Register Function
H
Shift register data advanced one bit
Latched
L
Shift register data advanced one bit
Transparent
H or L
L
No effect
Updated with current shift register contents
L
No effect
Latched all 12 bits
1
equals positive logic transition.
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