All input signals are specified with tr = tf = 1 ns (10" />
參數(shù)資料
型號: AD5428YRU-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 30/33頁
文件大?。?/td> 0K
描述: IC DAC 8BIT MULTIPLYING 20-TSSOP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1,000
設(shè)置時間: 30ns
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 3.3µW
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 21.3M
Data Sheet
AD5428/AD5440/AD5447
Rev. C | Page 5 of 32
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: 40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Limit at TMIN, TMAX
Unit
Conditions/Comments
Write Mode
t1
0
ns min
R/W to CS setup time
t2
0
ns min
R/W to CS hold time
t3
10
ns min
CS low time
t4
10
ns min
Address setup time
t5
0
ns min
Address hold time
t6
6
ns min
Data setup time
t7
0
ns min
Data hold time
t8
5
ns min
R/W high to CS low
t9
7
ns min
CS min high time
Data Readback Mode
t10
0
ns typ
Address setup time
t11
0
ns typ
Address hold time
t12
5
ns typ
Data access time
25
ns max
t13
5
ns typ
Bus relinquish time
10
ns max
Update Rate
21.3
MSPS
Consists of CS min high time, CS low time, and output
voltage settling time
1 Guaranteed by design and characterization, not subject to production test.
04462-002
DATA VALID
DATA
DACA/DACB
CS
R/W
t1
t3
t4
t10
t5
t8
t7
t11
t9
t2
t8
t2
t12
t13
Figure 2. Timing Diagram
04462-003
TO OUTPUT
PIN
VOH (MIN) + VOL (MAX)
200
μAI
OH
200
μAI
OL
2
CL
50pF
Figure 3. Load Circuit for Data Output Timing Specifications
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