VDD = 2.5 V to 5." />
參數(shù)資料
型號： AD5424YCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 24/29頁
文件大?。?/td> 0K
描述： IC DAC 8BIT MULTIPLYING 20-LFCSP
產(chǎn)品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 1
設置時間： 30ns
位數(shù)： 8
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 25µW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-VFQFN 裸露焊盤，CSP
供應商設備封裝： 20-LFCSP-VQ
包裝： 托盤
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 20.4M
配用： EVAL-AD5424EBZ-ND - BOARD EVALUATION FOR AD5424
Data Sheet
AD5424/AD5433/AD5445
Rev. D | Page 3 of 28
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: 40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions
STATIC PERFORMANCE
Resolution
8
Bits
Relative Accuracy
±0.25
LSB
Differential Nonlinearity
±0.5
LSB
Guaranteed monotonic
Resolution
10
Bits
Relative Accuracy
±0.5
LSB
Differential Nonlinearity
±1
LSB
Guaranteed monotonic
Resolution
12
Bits
Relative Accuracy
±1
LSB
Differential Nonlinearity
–1/+2
LSB
Guaranteed monotonic
Gain Error
±10
mV
Gain Error Temperature Coefficient1
±5
ppm FSR/°C
Output Leakage Current1
±10
nA
Data = 0×0000, TA = 25°C, IOUT1
±20
nA
Data = 0×0000, T = 40°C to +125°C, IOUT1
REFERENCE INPUT1
Reference Input Range
±10
V
VREF Input Resistance
8
10
12
k
Input resistance TC = –50 ppm/°C
RFB Resistance
8
10
12
k
Input resistance TC = –50 ppm/°C
Input Capacitance
Code Zero Scale
3
6
pF
Code Full Scale
5
8
pF
DIGITAL INPUTS/OUTPUT1
Input High Voltage, VIH
1.7
V
Input Low Voltage, VIL
0.6
V
Output High Voltage, VOH
VDD 1
V
VDD = 4.5 V to 5 V, ISOURCE = 200 A
VDD 0.5
V
VDD = 2.5 V to 3.6 V, ISOURCE = 200 A
Output Low Voltage, VOL
0.4
V
VDD = 4.5 V to 5 V, ISINK = 200 A
0.4
V
VDD = 2.5 V to 3.6 V, ISINK = 200 A
Input Leakage Current, IIL
1
A
Input Capacitance
4
10
pF
DYNAMIC PERFORMANCE1
Reference Multiplying Bandwidth
10
MHz
VREF = ±3.5 V; DAC loaded all 1s
Output Voltage Settling Time
VREF = ±3.5 V, RLOAD = 100 , DAC latch
alternately loaded with 0s and 1s
Measured to ±16 mV of full scale
30
60
ns
Measured to ±4 mV of full scale
35
70
ns
Measured to ±1 mV of full scale
80
120
ns
Digital Delay
20
40
ns
Interface delay time
10% to 90% Settling Time
15
30
ns
Rise and fall time, VREF = 10 V, RLOAD = 100
Digital-to-Analog Glitch Impulse
2
nV-s
1 LSB change around major carry, VREF = 0 V
Multiplying Feedthrough Error
DAC latch loaded with all 0s, VREF = ±3.5 V
70
dB
Reference = 1 MHz
48
dB
Reference = 10 MHz
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