
AD5410/AD5420
Data Sheet
Rev. F | Page 30 of 32
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-ADT
061708-
A
24
13
12
1
6.40 BSC
0.15
0.05
0.10 COPLANARITY
TOP VIEW
EXPOSED
PAD
(Pins Up)
BOTTOM VIEW
4.50
4.40
4.30
7.90
7.80
7.70
1.20 MAX
1.05
1.00
0.80
0.65
BSC
0.30
0.19
SEATING
PLANE
0.20
0.09
8°
0°
0.75
0.60
0.45
5.02
5.00
4.95
3.25
3.20
3.15
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 56. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP]
(RE-24)
Dimensions shown in millimeters
1
40
10
11
31
30
21
20
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
06-
01-
2012-
D
0.50
BSC
PIN 1
INDICATOR
4.50 REF
0.20 MIN
0.50
0.40
0.30
TOP VIEW
12° MAX
0.80 MAX
0.65 TYP
SEATING
PLANE
COPLANARITY
0.08
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
4.25
4.10 SQ
3.95
0.60 MAX
PIN 1
INDICATOR
6.10
6.00 SQ
5.90
5.85
5.75 SQ
5.65
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
EXPOSED
PAD
(BOTTOM VIEW)
Figure 57. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature Range
Resolution
TUE
Package Description
Package Option
AD5410AREZ
40°C to +85°C
12 Bits
0.3% Max
24-Lead TSSOP_EP
RE-24
AD5410AREZ-REEL7
40°C to +85°C
12 Bits
0.3% Max
24-Lead TSSOP_EP
RE-24
AD5410ACPZ-REEL
40°C to +85°C
12 Bits
0.3% Max
40-Lead LFCSP_VQ
CP-40-1
AD5410ACPZ-REEL7
40°C to +85°C
12 Bits
0.3% Max
40-Lead LFCSP_VQ
CP-40-1
AD5420AREZ
40°C to +85°C
16 Bits
0.15% Max
24-Lead TSSOP_EP
RE-24
AD5420AREZ-REEL7
40°C to +85°C
16 Bits
0.15% Max
24-Lead TSSOP_EP
RE-24
AD5420ACPZ-REEL
40°C to +85°C
16 Bits
0.15% Max
40-Lead LFCSP_VQ
CP-40-1
AD5420ACPZ-REEL7
40°C to +85°C
16 Bits
0.15% Max
40-Lead LFCSP_VQ
CP-40-1
EVAL-AD5420EBZ
Evaluation Board
1
Z = RoHS Compliant Part.