參數(shù)資料
型號: AD539KDZ
廠商: Analog Devices Inc
文件頁數(shù): 4/21頁
文件大?。?/td> 0K
描述: IC MULT/DIV DUAL CH LIN 16-CDIP
標準包裝: 1
功能: 模擬乘法器/除法器
位元/級數(shù): 雙象限
封裝/外殼: 16-CDIP(0.300",7.62mm)
供應商設備封裝: 16-CDIP 側(cè)面銅焊
包裝: 管件
AD539
Rev. B | Page 11 of 20
The power supplies to the AD539 can be as low as ±4.5 V and as
high as ±16.5 V. The maximum allowable range of the signal
inputs, VY, is approximately 0.5 V above +VS; the minimum
value is 2.5 V above VS. To accommodate the peak specified
inputs of ±4.2 V the supplies should be nominally +5 V and
7.5 V. Although there is no performance advantage in raising
supplies above these values, it may often be convenient to use
the same supplies as for the op amps. The AD539 can tolerate
the excess voltage with only a slight effect on dc accuracy but
dissipation at ±16.5 V can be as high as 535 mW, and some
form of heat sink is essential in the interests of reliability.
TRANSFER FUNCTION
In using any analog multiplier or divider, careful attention must
be paid to the matter of scaling, particularly in computational
applications. To be dimensionally consistent, a scaling voltage
must appear in the transfer function, which, for each channel
of the AD539 in the standard multiplier configuration (see
VW = VXVY/VU
where the VX and VY inputs, the VW output, and the scaling
voltage, VU, are expressed in a consistent unit, usually volts.
In this case, VU is fixed by the design to be 1 V and it is often
acceptable in the interest of simplification to use the less rigorous
expression
VW = VXVY
where it is understood that all signals must be expressed in volts,
that is, they are rendered dimensionless by division by 1 V.
The accuracy specifications for VU allow the use of either of the
two feedback resistors supplied with each channel, because
these are very closely matched, or they can be used in parallel to
halve the gain (double the effective scaling voltage), when
VW = VXVY/2
When an external load resistor, RL, is used, the scaling is no
longer exact because the internal thin film resistors, although
trimmed to high ratiometric accuracy, have an absolute
tolerance of 20%. However, the nominal transfer function is
VW = VXVY/VU
where the effective scaling voltage, VU’, can be calculated for
each channel using the formula
VU’ = VU (5RL + 6.25)/RL
where RL is expressed in kilohms. For example, when RL =
100 Ω, VU’ = 67.5 V. Table 5 provides more detailed data for the
case where both channels are used in parallel. The AD539 can
also be used with no external load (CHAN2 OUTPUT, Pin 11,
or CHAN1 OUTPUT, Pin 14, open circuit), when VU’ is
precisely 5 V.
DUAL SIGNAL CHANNELS
The signal voltage inputs, VY1 and VY2, have nominal full-scale
(FS) values of ±2 V with a peak range to ±4.2 V (using a negative
supply of 7.5 V or greater). For video applications where
differential phase is critical, a reduced input range of ±1 V is
recommended, resulting in a phase variation of typically ±0.2°
at 3.579 MHz for full gain. The input impedance is typically
400 kΩ shunted by 3 pF. Signal channel distortion is typically
well under 0.1% at 10 kHz and can be reduced to 0.01% by using
the channels differentially.
COMMON CONTROL CHANNEL
The control channel accepts positive inputs, VX, from 0 V to 3 V
FS, ±3.3 V peak. The input resistance is 500 Ω. An external,
grounded capacitor determines the small-signal bandwidth and
recovery time of the control amplifier; the minimum value of
3 nF allows a bandwidth at midgain of about 5 MHz. Larger
compensation capacitors slow the control channel but improve
the high frequency performance of the signal channels.
FLEXIBLE SCALING
Using either one or two external op amps in conjunction with
the on-chip 6 kΩ scaling resistors (see Figure 19), the output
currents (nominally ±1 mA FS, ±2.25 mA peak) can be
converted to voltages with accurate transfer functions of VW =
VXVY/2, VW = VXVY, or VW = 2VXVY (where the VX and VY
inputs and VW output are expressed in volts), with correspond-
ing full-scale outputs of ±3 V, ±6 V, and ±12 V. Alternatively,
low impedance grounded loads can be used to achieve the full
signal bandwidth of 60 MHz, in which mode the scaling is less
accurate.
VX
VY1
W1
VW1 = –VXVY1
VW2 = –VXVY2
Z1
EXTRNAL
OP AMPS
VY2
Z2
W2
096
79-
019
CHAN1
MULTIPLY
CHAN2
MULTIPLY
Figure 19. Block Diagram Showing Scaling Resistors and External Op Amps
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