參數(shù)資料
型號： AD5383BSTZ-5
廠商： Analog Devices Inc
文件頁數(shù)： 19/40頁
文件大?。?/td> 0K
描述： IC DAC 12BIT 32CH 5V 100-LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： AD5381,3 Redesign Change 24/Oct/2011
設(shè)計資源： 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5383 (CN0014)
AD5383 Channel Monitor Function (CN0015)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時間： 6µs
位數(shù)： 12
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 32
電壓電源： 單電源
功率耗散（最大）： 65mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
輸出數(shù)目和類型： 32 電壓，單極；32 電壓，雙極
采樣率（每秒）： 167k
AD5383
Data Sheet
Rev. C | Page 26 of 40
INTERFACES
The AD5383 contains both parallel and serial interfaces.
Furthermore, the serial interface can be programmed to be
SPI-, DSP-, MICROWIRE-, or I2C-compatible. The SER/PAR
pin selects parallel and serial interface modes. In serial mode,
the SPI/I2C pin is used to select DSP, SPI, MICROWIRE, or I2C
interface mode.
The devices use an internal FIFO memory to allow high speed
successive writes in parallel interface mode. The user can con-
tinue writing new data to the device while write instructions are
being executed. The BUSY signal indicates the current status of
the device, going low while instructions in the FIFO are being
executed. In parallel mode, up to 128 successive instructions
can be written to the FIFO at maximum speed. When the FIFO
is full, any further writes to the device are ignored.
To minimize both the power consumption of the device and the
on-chip digital noise, the active interface only powers up fully
when the device is being written to, that is, on the falling edge
of WR or the falling edge of SYNC.
DSP-, SPI-, MICROWIRE-COMPATIBLE SERIAL
INTERFACES
The serial interface can be operated with a minimum of three
wires in standalone mode or four wires in daisy-chain mode.
Daisy-chaining allows many devices to be cascaded together to
increase system channel count. The SER/PAR pin must be tied
high and the SPI/I2C pin (Pin 97) should be tied low to enable
the DSP-/SPI-/MICROWIRE-compatible serial interface. In
serial interface mode, the user does not need to drive the
parallel input data pins. The serial interface’s control pins are:
SYNC, DIN, SCLK—Standard 3-wire interface pins.
DCEN—Selects standalone mode or daisy-chain mode.
SDO—Data out pin for daisy-chain mode.
Figure 3 and Figure 5 show timing diagrams for a serial write to
the AD5383 in standalone and daisy-chain modes. The 24-bit
data-word format for the serial interface is shown in Table 18.
A/B. When toggle mode is enabled, this pin selects whether the
data write is to the A or B register. With toggle disabled, this bit
should be set to zero to select the A data register.
R/W is the read or write control bit.
A4 to A0 address the input channels.
REG1 and REG0 select the register to which data is written, as
shown in Table 10.
DB11 to DB0 contain the input data-word.
X is a don’t care condition.
Standalone Mode
By connecting the DCEN (daisy-chain enable) pin low, stand-
alone mode is enabled. The serial interface works with both a
continuous and a noncontinuous serial clock. The first falling
edge of SYNC starts the write cycle and resets a counter that
counts the number of serial clocks to ensure that the correct
number of bits are shifted into the serial shift register. Any
further edges on SYNC, except for a falling edge, are ignored
until 24 bits are clocked in. Once 24 bits have been shifted in,
the SCLK is ignored. In order for another serial transfer to take
place, the counter must be reset by the falling edge of SYNC.
Table 18. 40-Channel, 12-Bit DAC Serial Input Register Configuration
MSB
LSB
A/B
R/W
0
A4
A3
A2
A1
A0
REG1
REG0
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
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