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參數資料
| 型號： | AD5381BSTZ-3-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 20/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 40CH 3V 100-LQFP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產品變化通告： | AD5381,3 Redesign Change 24/Oct/2011 |
| 設計資源： | 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5381 (CN0010) AD5381 Channel Monitor Function (CN0013) |
| 標準包裝： | 1 |
| 設置時間： | 6µs |
| 位數： | 12 |
| 數據接口： | 串行，并聯(lián) |
| 轉換器數目： | 40 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 80mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 標準包裝 |
| 輸出數目和類型： | 40 電壓，單極 |
| 采樣率（每秒）： | 167k |
| 其它名稱： | AD5381BSTZ-3-REELDKR |
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Data Sheet
AD5381
Rev. D | Page 27 of 40
Daisy-Chain Mode
For systemsthat contain several devices, theSDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interfacelines.
By connecting the DCEN (daisy-chain enable)pin high, daisy-
chain mode is enabled. Thefirst falling edge of SYNC starts the
write cycle. The SCLK is continuously applied to the input shift
register when SYNC is low. If more than 24clock pulses are
applied, the data ripplesout of the shift register and appears
on the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO
of the first device to the DIN input on the next device in the
chain, a multidevice interface is constructed. Twenty-four clock
pulses are requiredfor each device in the system.Therefore, the
total number of clockcycles must equal 24N, where N is the
total number of AD538x devices in the chain.
When the serial transferto all devices is complete, SYNC is
taken high. This latches the input data in each device in the
daisy-chain and prevents further datafrombeing clocked
into the input shift register.
If SYNC is taken high before 24clocks are clocked into the part,
this is considered a bad frameand the data is discarded.
The serial clock can be either a continuous or a gated clock. A
continuous SCLK sourcecan only be used if it can be arranged
that SYNC is held low for the correct number of clockcycles. In
gated clock mode, a burst clockcontaining the exact number of
clock cycles must be used and SYNC must betaken high after
the final clock to latch the data.
Readback Mode
Readbackmodeis invoked by settingthe R/Wbit = 1in the
serial input register write. With R/W= 1, Bits A5to A0, in
association with Bits REG1 and REG0, select theregister tobe
read. The remainingdatabitsin the write sequencearedon’t
cares. Duringthe next SPIwrite,the data appearing on the
SDO output will contain thedata fromthe previously
addressedregister.
For a read of a single register, the NOP commandcan be used
in clocking out the data from the selected register on SDO.
Figure 30 shows the readbacksequence. For example, to read
backthe m register of Channel 0 on the AD5381, the following
sequence shouldbe implemented. First, write0x404XXX to the
AD5381 input register. This configures the AD5381 for read
mode with the m register of Channel 0 selected. Notethat Data
Bits DB11 to DB0 are don’t cares. Follow this with a second
write, a NOP condition, 0x000000.
During this write, the data from the m registeris clocked out on
the DOUT line, that is, data clocked out will contain the data
from the m register in Bit DB11 to Bit DB0, and the top 10 bits
contain the address information as previously written. In
readbackmode,the SYNC signalmust frame the data. Data is
clocked out on the rising edge of SCLK and is valid on the
falling edge of the SCLK signal. If the SCLK idles high between
the write and read operationsof a readbackoperation, the first
bit of data is clocked out on the falling edge of SYNC.
03732-030
24
48
SCLK
SYNC
DIN
SDO
UNDEFINED
SELECTED REGISTER DATA CLOCKED OUT
NOP CONDITION
INPUT WORD SPECIFIES REGISTER TO BE READ
DB23
DB0
DB23
DB0
DB23
Figure 30. Serial Readback Operation
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相關代理商/技術參數 |
參數描述 |
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| AD5381BSTZ-5 | 功能描述:IC DAC 12BIT 40CH 5V 100-LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數:8 數據接口:串行 轉換器數目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5381BSTZ-5-REEL | 功能描述:IC DAC 12BIT 40CH 5V 100-LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數:8 數據接口:串行 轉換器數目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5382BST-3 | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:32/40-CHANNEL 3V/5V SINGLE SUPPLY 12/14-BIT VOUT DAC - Bulk |
| AD5382BST-3-REEL | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP T/R |
| AD5382BST-5 | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:32-CHN 5V SINGLE SUPPLY 14-BIT VOUT I.C. - Bulk |
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