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參數(shù)資料
| 型號： | AD536AKQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 552K |
| 描述： | IC TRUE RMS/DC CONV 14CDIP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 電流 - 電源： | 1.2mA |
| 電源電壓： | 5.0V ~ 36V，±3.0V ~ 18V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-CERDIP |
| 包裝： | 管件 |
Data Sheet
AD536A
Rev. E | Page 13 of 16
The primary disadvantage in using a large C
AV
to remove ripple
is that the settling time for a step change in input level is
increased proportionately. Figure 19 illustrates that the
relationship between C
AV
and 1% settling time is 115 ms for
each microfarad of C
AV
. The settling time is twice as great for
decreasing signals as it is for increasing signals. The values in
Figure 19 are for decreasing signals. Settling time also increases
for low signal levels, as shown in Figure 20.
10
100
1k
10k
0.1
1
10
100
0.01
1
100k
INPUT FREQUENCY (Hz)
0.1
1
10
100
0.01
0
.
0
1
%
E
R
R
O
R
0
.
1
%
E
R
R
O
R
1
0
%
E
R
R
O
R
1
%
E
R
R
O
R
PERCENT DC ERROR AND PERCENT RIPPLE PEAK
VALUES FOR C
AV
AND
1% SETTLING TIME
FOR STATED % OF READING
AVERAGING ERROR
1
ACCURACY ?20% DUE TO
COMPONENT TOLERANCE
Figure 19. Error/Settling Time Graph for Use with the Standard RMS
Connection (See Figure 13 Through Figure 15)
10m
100m
1
7.5
10.0
5.0
1m
10
rms INPUT LEVEL V
1.0
2.5
Figure 20. Settling Time vs. Input Level
A better method to reduce output ripple is the use of a postfilter.
Figure 21 shows a suggested circuit. If a single-pole filter is used
(C3 removed, R
X
shorted) and C2 is approximately twice the
value of C
AV
, the ripple is reduced, as shown in Figure 22, and
settling time is increased. For example, with C
AV
= 1 礔 and C2
= 2.2 糉, the ripple for a 60 Hz input is reduced from 10% of
reading to approximately 0.3% of reading.
The settling time, however, is increased by approximately a
factor of 3. Therefore, the values of C
AV
and C2 can be reduced
to permit faster settling times while still providing substantial
ripple reduction.
The two-pole postfilter uses an active filter stage to provide
even greater ripple reduction without substantially increasing
the settling times over a circuit with a one-pole filter. The values
of C
AV
, C2, and C3 can then be reduced to allow extremely fast
settling times for a constant amount of ripple. Caution should
be exercised in choosing the value of C
AV
, because the dc error
is dependent on this value and is independent of the postfilter.
For a more detailed explanation of these topics, refer to the RMS to
DC Conversion Application Guide, 2nd Edition, available online
from Analog Devices, Inc., at www.analog.com.
C2
V
IN
C
AV
+V
S
14
13
12
11
10
9
8
1
2
3
4
5
6
7
AD536A
25k&
ABSOLUTE
VALUE
SQUARER/
DIVIDER
CURRENT
MIRROR
V
S
Rx
24k&
+
+
C3
1
V
rms
OUT
1
FOR SINGLE POLE, SHORT Rx, REMOVE C3.
V
IN
NC
V
S
C
AV
+V
S
NC
NC
NC
dB
COM
BUF OUT
R
L
BUF IN
I
OUT
BUF
Figure 21. Two-Pole Postfilter
1
1k
100
10k
0.1
10
10
PEAK-TO-PEAK RIPPLE
C
AV
= 1礔
DC ERROR
C
AV
= 1礔
(ALL FILTERS)
PEAK-TO-PEAK RIPPLE
C
AV
= 1礔
C2 = C3 = 2.2礔 (TWO-POLE)
Rx = 0&
PEAK-TO-PEAK
RIPPLE (ONE POLE)
C
AV
= 1礔, C2 = 2.2礔
FREQUENCY (Hz)
Figure 22. Performance Features of Various Filter Types
(See Figure 13 to Figure 15 for Standard RMS Connection)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD536ASCHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Circuit True RMS-to-DC Converter |
| AD536ASD | 功能描述:IC TRUE RMS/DC CONV 14-CDIP RoHS:否 類別:集成電路 (IC) >> PMIC - RMS 至 DC 轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:46 系列:- 電流 - 電源:1.2mA 電源電壓:±18 V，36 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC W 包裝:管件 |
| AD536ASD/883B | 功能描述:直流/直流開關(guān)轉(zhuǎn)換器 RMS/DC CONVERTER IC RoHS:否 制造商:STMicroelectronics 最大輸入電壓:4.5 V 開關(guān)頻率:1.5 MHz 輸出電壓:4.6 V 輸出電流:250 mA 輸出端數(shù)量:2 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT |
| AD536ASD883B | 制造商:ANALOG DEV 功能描述:DIP-14PIN GOLD |
| AD536ASE | 制造商:Rochester Electronics LLC 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
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