參數(shù)資料
型號: AD5363BSTZ
廠商: Analog Devices Inc
文件頁數(shù): 24/29頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 8CH SERIAL 52-LQFP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1
設置時間: 20µs
位數(shù): 14
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 8
電壓電源: 雙 ±
功率耗散(最大): 209mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 52-LQFP
供應商設備封裝: 52-LQFP(10x10)
包裝: 托盤
輸出數(shù)目和類型: 8 電壓,單極;8 電壓,雙極
采樣率(每秒): *
配用: EVAL-AD5363EBZ-ND - BOARD EVALUATION FOR AD5363
AD5362/AD5363
Rev. A | Page 3 of
28
GENERAL DESCRIPTION
The AD5362/AD5363 contain eight 16-/14-bit DACs in a single
52-lead LQFP package or 56-lead LFCSP package. The devices
provide buffered voltage outputs with a span of 4× the reference
voltage. The gain and offset of each DAC can be independently
trimmed to remove errors. For even greater flexibility, the device
is divided into two groups of four DACs, and the output range
of each group can be independently adjusted by an offset DAC.
The AD5362/AD5363 offer guaranteed operation over a wide
supply range with VSS from 16.5 V to 4.5 V and VDD from 8 V
to 16.5 V. The output amplifier headroom requirement is 1.4 V,
operating with a load current of 1 mA.
The AD5362/AD5363 have a high speed 4-wire serial interface
that is compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards and can handle clock speeds of up to
50 MHz. All the outputs can be updated simultaneously by
taking the LDAC input low. Each channel has a programmable
gain and an offset adjust register.
Each DAC output is gained and buffered on chip with respect
to an external SIGGNDx input. The DAC outputs can also be
switched to SIGGNDx via the CLR pin.
Table 1. High Channel Count Bipolar DACs
Model
Resolution (Bits)
Nominal Output Span
Output Channels
Linearity Error (LSB)
16
4 × VREF (20 V)
16
±4
14
4 × VREF (20 V)
16
±1
AD5362
16
4 × VREF (20 V)
8
±4
AD5363
14
4 × VREF (20 V)
8
±1
16
4 × VREF (12 V)
40
±4
14
4 × VREF (12 V)
40
±1
16
4 × VREF (12 V)
32
±4
14
4 × VREF (12 V)
32
±1
14
±8.75 V
32
±3
14
±8.75 V
40
±3
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