參數(shù)資料
型號: AD5363BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 5/29頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 8CH SERIAL 56-LFCSP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時間: 20µs
位數(shù): 14
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 8
電壓電源: 雙 ±
功率耗散(最大): 209mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 56-LFCSP-VQ(8x8)
包裝: 托盤
輸出數(shù)目和類型: 8 電壓,單極;8 電壓,雙極
采樣率(每秒): *
配用: EVAL-AD5363EBZ-ND - BOARD EVALUATION FOR AD5363
AD5362/AD5363
Rev. A | Page 12 of
28
Pin No.
Mnemonic
Description
LQFP
LFCSP
33
35
TEMP_OUT
Provides an output voltage proportional to the chip temperature, typically
1.46 V at 25°C with an output variation of 4.4 mV/°C.
38
40
SIGGND0
Reference Ground for DAC 0 to DAC 3. VOUT0 to VOUT3 are referenced to this
voltage.
43, 51
45, 53
DGND
Ground for All Digital Circuitry. Both DGND pins should be connected to the
DGND plane.
44, 50
46, 52
DVCC
Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 μF
ceramic capacitors and 10 μF capacitors.
45
47
SYNC
Active Low or SYNC Input for SPI Interface. This is the frame synchronization
signal for the SPI serial interface. See
,
, and the
section for more details.
46
48
SCLK
Serial Clock Input for SPI Interface. See Figure 4, Figure 5, and the Serial Interface
section for more details.
47
49
SDI
Serial Data Input for SPI Interface. See Figure 4, Figure 5, and the Serial Interface
section for more details.
48
50
PEC
Packet Error Check Output. This is an open-drain output with a 50 kΩ pull-up
that goes low if the packet error check fails.
49
51
SDO
Serial Data Output for SPI Interface. See Figure 4, Figure 5, and the Serial
Interface section for more details.
52
54
AGND
Ground for All Analog Circuitry. The AGND pin should be connected to the
AGND plane.
Exposed Paddle
EP
Exposed Paddle. Connect to VSS.
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