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參數(shù)資料
| 型號： | AD53508JP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DUAL PARAMETRIC MEASURE44PLCC |
| 標準包裝： | 1 |
| 應(yīng)用： | 測試設(shè)備 |
| 接口： | 模擬 |
| 電源電壓： | 14 V ~ 15.75 V |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
AD53508
–5–
REV. A
Table I. Data Table
Data Latch Bits
S13,
S15,
S1
S2
S3
S4
S5
S6
S7
S9
S17
S8
S10
S14
S16
S11
S12
S18
Voltage Force/Current Measure
Irange 0
On
Off
OnOnOff
On
Off
OnOnOnOff
Off
On
Irange 1
On
Off
OnOnOff
On
Off
OnOnOff
On
Off
On
Integrate Range
On
Off
OnOnOff
On
Off
OnOnOff
Off
OnOnOn
Integrate
On
Off
On
Off
On
Off
On
Off
On
Hold/Measure
On
Off
OnOnOff
On
Off
OnOnOff
Off
On
Current Force/Voltage Measure
Irange 0
On
Off
On
Off
On
Off
On
Irange 1
On
Off
On
Off
On
Off
On
Off
On
Disable Mode: Output Connected
XXXOn
Off
On
Off
On
X
On
Off
On
Verify/Voltage Force
On
Off
OnOff
On
Off
OnOnOnOff
Off
On
Verify/Current Force
On
Off
OnOff
On
Off
OnOnOnOff
Off
On
Disconnect
XXXOn
Off
XXOn
Off
On
Off
On
Off
DAC2 Select: Enabled
XXXXXOff
On
XXXXXXXXX
CAPACITOR
CHARGE
INTEGRATE*
HOLD*
INTEGRATE
HOLD
DISCHARGE
CAPACITOR
* = ACTIVE LO
Figure 1. Integrate/Current Measure Timing Diagram
Table II. Truth Table
* = Active LO
FV/MI 2 mA
FV/MI 200 mA
FV/MI Integrate DAC1
FV/MI Integrate DAC 2
FI/MV 2 mA
FI/MV 200
A
FV/Verify
FI/Verify
Disconnect
Disable
Control
Voltage
Inte-
Voltage
Inte-
Output
Input
DAC1
DAC2
DAC1
DAC2
Settle
grate
Hold
Settle
grate
Hold
DAC1
DAC2
DAC1
DAC2
DAC1
DAC2
DAC1
DAC2
Connected
M_CON
*
LO
X
VERIFY
*
HI
LO
X
FORCE_I
*
HI
LO
HI
LO
X
FORCE_EN
*
LO
X
HI
DAC1_SEL
*
LO
HI
LO
HI
LO
HI
LO
HI
LO
HI
LO
HI
LO
HI
X
INTEG
*
HI
LO
HI
LO
HI
X
HOLD
*
HI
LO
HI
LO
HI
X
I_RANGE0
*
LO
HI
LO
HI
X
I_RANGE1
*
HI
LO
HI
LO
X
OUTPUT_CON
*
LO
HI
LO
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