(VDD = 2.5 V to 5.5 V, V
參數(shù)資料
型號(hào)： AD5344BRU
廠商： Analog Devices Inc
文件頁數(shù)： 12/20頁
文件大?。?/td> 0K
描述： IC DAC 12BIT QUAD VOUT 28-TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 50
設(shè)置時(shí)間： 8µs
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 單電源
功率耗散（最大）： 4.5mW
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 管件
輸出數(shù)目和類型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： 125k
REV. 0
–2–
AD5334/AD5335/AD5336/AD5344–SPECIFICATIONS
(VDD = 2.5 V to 5.5 V, VREF = 2 V. RL = 2 k
to GND; CL =200 pF to GND; all specications TMIN to TMAX unless otherwise noted.)
B Version
2
Parameter
1
Min
Typ
Max
Unit
Conditions/Comments
DC PERFORMANCE
3, 4
AD5334
Resolution
8
Bits
Relative Accuracy
±0.15
±1
LSB
Differential Nonlinearity
±0.02
±0.25
LSB
Guaranteed Monotonic By Design Over All Codes
AD5335/AD5336
Resolution
10
Bits
Relative Accuracy
±0.5
±4
LSB
Differential Nonlinearity
±0.05
±0.5
LSB
Guaranteed Monotonic By Design Over All Codes
AD5344
Resolution
12
Bits
Relative Accuracy
±2
±16
LSB
Differential Nonlinearity
±0.2
±1
LSB
Guaranteed Monotonic By Design Over All Codes
Offset Error
±0.4
±3
% of FSR
Gain Error
±0.1
±1
% of FSR
Lower Deadband
5
10
60
mV
Lower Deadband Exists Only if Offset Error Is Negative
Upper Deadband
10
60
mV
VDD = 5 V. Upper Deadband Exists Only if VREF = VDD
Offset Error Drift
6
–12
ppm of FSR/
°C
Gain Error Drift
6
–5
ppm of FSR/
°C
DC Power Supply Rejection Ratio6
–60
dB
V
DD =
±10%
DC Crosstalk
6
200
VRL = 2 k to GND, 2 k to VDD; CL = 200 pF to GND;
Gain = 0
DAC REFERENCE INPUT
6
VREF Input Range
0.25
VDD
V
VREF Input Impedance
180
k
Gain = 1. Input Impedance = RDAC (AD5336/AD5344)
90
k
Gain = 2. Input Impedance = RDAC (AD5336)
90
k
Gain = 1. Input Impedance = RDAC (AD5334/AD5335)
45
k
Gain = 2. Input Impedance = RDAC (AD5334)
Reference Feedthrough
–90
dB
Frequency = 10 kHz
Channel-to-Channel Isolation
–90
dB
Frequency = 10 kHz
OUTPUT CHARACTERISTICS
6
Minimum Output Voltage
4, 7
0.001
V min
Rail-to-Rail Operation
Maximum Output Voltage
4, 7
VDD – 0.001
V max
DC Output Impedance
0.5
Short Circuit Current
50
mA
VDD = 5 V
20
mA
VDD = 3 V
Power-Up Time
2.5
s
Coming Out of Power-Down Mode. VDD = 5 V
5
s
Coming Out of Power-Down Mode. VDD = 3 V
LOGIC INPUTS
6
Input Current
±1
A
VIL, Input Low Voltage
0.8
V
VDD = 5 V
± 10%
0.6
V
VDD = 3 V
± 10%
0.5
V
VDD = 2.5 V
VIH, Input High Voltage
2.4
V
VDD = 5 V
± 10%
2.1
V
VDD = 3 V
± 10%
2.0
V
VDD = 2.5 V
Pin Capacitance
3.5
pF
POWER REQUIREMENTS
VDD
2.5
5.5
V
IDD (Normal Mode)
All DACs active and excluding load currents.
VDD = 4.5 V to 5.5 V
600
900
AVIH = VDD, VIL = GND.
VDD = 2.5 V to 3.6 V
500
700
AI
DD increases by 50
A at V
REF > VDD – 100 mV.
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
0.2
1
A
VDD = 2.5 V to 3.6 V
0.08
1
A
NOTES
1See Terminology section.
2Temperature range: B Version: –40
°C to +105°C; typical specications are at 25°C.
3Linearity is tested using a reduced code range: AD5334 (Code 8 to 255); AD5335/AD5336 (Code 28 to 1023); AD5344 (Code 115 to 4095).
4DC specications tested with outputs unloaded.
5This corresponds to x codes. x = Deadband voltage/LSB size.
6Guaranteed by design and characterization, not production tested.
7In order for the amplier output to reach its minimum voltage, Offset Error must be negative. In order for the amplier output to reach its maximum voltage, V
REF = VDD and
“Offset plus Gain” Error must be positive.
Specications subject to change without notice.
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