VDD = 2" />
參數(shù)資料
型號: AD5330BRUZ
廠商: Analog Devices Inc
文件頁數(shù): 24/28頁
文件大小: 0K
描述: IC DAC 8BIT SNGL VOUT 20-TSSOP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 75
設置時間: 6µs
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 1.25mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 167k
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 5 of 28
TIMING CHARACTERISTICS1, 2, 3
VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Condition/Comments
t1
0
ns min
CS to WR setup time.
t2
0
ns min
CS to WR hold time.
t3
20
ns min
WR pulse width.
t4
5
ns min
Data, GAIN, BUF, HBEN setup time.
t5
4.5
ns min
Data, GAIN, BUF, HBEN hold time.
t6
5
ns min
Synchronous mode; WR falling to LDAC falling.
t7
5
ns min
Synchronous mode; LDAC falling to WR rising.
t8
4.5
ns min
Synchronous mode; WR rising to LDAC rising.
t9
5
ns min
Asynchronous mode; LDAC rising to WR rising.
t10
4.5
ns min
Asynchronous mode; WR rising to LDAC falling.
t11
20
ns min
LDAC pulse width.
t12
20
ns min
CLR pulse width.
t13
50
ns min
Time between WR cycles.
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
CS
WR
DATA,
GAIN,
BUF,
HBEN
LDAC1
LDAC2
CLR
NOTES:
1SYNCHRONOUS LDAC UPDATE MODE
2ASYNCHRONOUS LDAC UPDATE MODE
t1
t2
t3
t4
t6
t7
t9
t10
t11
t12
t8
t5
t13
06
85
2-
00
2
Figure 2. Parallel Interface Timing Diagram
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