At 25°C, VS = ±15 V, R ≥ 2 k V
參數(shù)資料
型號: AD532SD
廠商: Analog Devices Inc
文件頁數(shù): 12/17頁
文件大小: 0K
描述: IC MULTIPLIER +/-10V 14-CDIP
標(biāo)準(zhǔn)包裝: 1
功能: 模擬乘法器/除法器
位元/級數(shù): 四象限
封裝/外殼: 14-CDIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 14-CDIP
包裝: 管件
AD532
Rev. D | Page 3 of 16
SPECIFICATIONS
At 25°C, VS = ±15 V, R ≥ 2 k VOS grounded, unless otherwise noted.
Table 1.
AD532J
AD532K
AD532S
Model
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
MULTIPLIER PERFORMANCE
Transfer Function
V
Y
X
10
)
(
)
(
2
1
2
1
V
Y
X
10
)
(
)
(
2
1
2
1
V
Y
X
10
)
(
)
(
2
1
2
1
Total Error
–10 V ≤ X, Y ≤ +10 V
±1.5
±2.0
±0.7
±1.0
±0.5
±1.0
%
TA = Minimum to Maximum
±2.5
±1.5
±4.0
%
Total Error vs. Temperature
±0.04
±0.03
±0.01
±0.04
%/°C
Supply Rejection
±15 V ±10%
±0.05
%/%
Nonlinearity, X
X = 20 V p-p, Y = 10 V
± 0.8
±0.5
%
Nonlinearity, Y
Y = 20 V p-p, X = 10 V
±0.3
±0.2
%
Feedthrough, X
Y nulled, X = 20 V p-p 50 Hz
50
200
30
100
30
100
mV
Feedthrough, Y (X Nulled,
30
150
25
80
25
80
mV
Y = 20 V p-p 50 Hz)
Feedthrough vs. Temperature
2.0
1.0
mV p-p/°C
Feedthrough vs. Power Supply
±0.25
mV/%
DYNAMICS
Small Signal BW
VOUT = 0.1 rms
1
MHz
1% Amplitude Error
75
kHz
Slew Rate
VOUT 20 p-p
45
V/μs
Settling Time
to 2%, ΔVOUT = 20 V
1
μs
NOISE
Wideband Noise
0.6
mV (rms)
f = 5 Hz to 10 kHz
f = 5 Hz to 5 MHz
3.0
mV (rms)
OUTPUT
Voltage Swing
±10
±13
±10
±13
±10
±13
V
Impedance
f ≤ 1 kHz
1
Offset Voltage
±40
±30
mV
Offset Voltage vs. Temperature
0.7
2.0
mV/°C
Offset Voltage vs. Supply
±2.5
mV/%
INPUT AMPLIFIERS (X, Y, and Z)
Signal Voltage Range
Differential or CM
operating differential
±10
V
CMRR
40
50
dB
Input Bias Current
X, Y Inputs
3
1.5
4
1.5
4
μA
X, Y Inputs TMIN to TMAX
10
8
±15
μA
Z Input
±10
±5
±15
±5
μA
Z Input TMIN to TMAX
±30
±25
μA
Offset Current
±0.3
±0.1
μA
Differential Resistance
10
M
DIVIDER PERFORMANCE
Transfer Function
Xl > X2
10 V Z/(X1 X2)
Total Error
VX = 10 V, 10 V ≤ VZ
+10 V
±2
±1
%
VX = 1 V, 10 V ≤ VZ
+10 V
±4
±3
%
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