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參數(shù)資料
| 型號： | AD5322BRMZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL 10MSOP T/R |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 設置時間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 2.5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 125k |
AD5302/AD5312/AD5322
Rev. D | Page 16 of 24
POWER-DOWN MODES
The AD5302/AD5312/AD5322 have very low power consump-
tion, dissipating only 0.7 mW with a 3 V supply and 1.5 mW
with a 5 V supply. Power consumption can be further reduced
when the DACs are not in use by putting them into one of three
power-down modes, which are selected by Bit 13 and Bit 12
(PD1 and PD0) of the control word. Table 7 shows how the
state of the bits corresponds to the mode of operation of that
particular DAC.
Table 7. PD1/PD0 Operating Modes
PD1
PDO
Operating Mode
0
Normal Operation
0
1
Power-Down (1 kΩ Load to GND)
1
0
Power-Down (100 kΩ Load to GND)
1
Power-Down (High Impedance Output)
When both bits are set to 0, the DACs work normally with
their normal power consumption of 300 μA at 5 V. However,
for the three power-down modes, the supply current falls to
200 nA at 5 V (50 nA at 3 V). Not only does the supply current
drop, but the output stage is also internally switched from the
output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode and provides a
defined input condition for whatever is connected to the output
of the DAC amplifier. There are three different options.
The output is connected internally to GND through a
1 kΩ resistor,
The output is connected internally to GND through a
100 kΩ resistor, or
The output is left open-circuited (three-state).
The output stage is illustrated in Figure 33.
The bias generator, the output amplifier, the resistor string,
and all other associated linear circuitry are shut down when
the power-down mode is activated. However, the contents of
the registers are unaffected when in power-down. The time to
exit power-down is typically 2.5 μs for VDD = 5 V and 5 μs when
RESISTOR-
STRING DAC
AMPLIFIER
VOUT
00
92
8-
03
3
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 33. Output Stage During Power-Down
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| AD5323ARUZ | 功能描述:IC DAC 12BIT DUAL R-R 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 標準包裝:47 系列:- 設置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
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