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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD5274BRMZ-100-RL7 |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 2/28闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC RHEOSTAT 5V 50-TP 256 10MSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1,000 |
| 鎺ョ墖锛� | 256 |
| 闆婚樆锛堟瓙濮嗭級锛� | 100k |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 婧害绯绘暩(sh霉)锛� | 妯�(bi膩o)婧�(zh菙n)鍊� 5 ppm/°C |
| 瀛樺劜鍣ㄩ鍨嬶細 | 闈炴槗澶� |
| 鎺ュ彛锛� | I²C |
| 闆绘簮闆诲锛� | 2.7 V ~ 5.5 V锛�±2.5 V ~ 2.75 V |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 10-TFSOP锛�10-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 10-MSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
绗�1闋�鐣�(d膩ng)鍓嶇2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�
AD5272/AD5274
Data Sheet
Rev. D | Page 10 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 1
VSS
2
A
3
W
4
10
9
8
SCL
ADDR
7
5
EXT_CAP
SDA
6
GND
AD5272/
AD5274
TOP VIEW
(Not to Scale)
RESET
08
07
6-
0
4
Figure 4. MSOP Pin Configuration
ADDR
VDD 1
VSS
2
A
3
W
4
RESET
10
9
8
SCL
7
5
EXT_CAP
SDA
6 GND
NOTES
1. THE EXPOSED PAD IS LEFT FLOATING
OR IS TIED TO VSS.
AD5272/
AD5274
(EXPOSED
PAD)
08
07
6
-04
0
Figure 5. LFCSP Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Positive Power Supply. Decouple this pin with 0.1 渭F ceramic capacitors and 10 渭F capacitors.
2
A
Terminal A of RDAC. VSS 鈮� VA 鈮� VDD.
3
W
Wiper terminal of RDAC. VSS 鈮� VW 鈮� VDD.
4
VSS
Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 渭F ceramic capacitors
and 10 渭F capacitors.
5
EXT_CAP
External Capacitor. Connect a 1 渭F capacitor between EXT_CAP and VSS. This capacitor must have a voltage
rating of 鈮�7 V.
6
GND
Ground Pin, Logic Ground Reference.
7
RESET
Hardware Reset Pin. Refreshes the RDAC register with the contents of the 50-TP memory register. Factory
default loads midscale until the first 50-TP wiper memory location is programmed. RESET is active low. Tie RESET
to VDD if not used.
8
SDA
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input registers. It is
a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.
9
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input registers.
10
ADDR
Tristate Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 11).
EPAD
Exposed Pad
(LFCSP Only)
Leave floating or tie to VSS.
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