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| 型號： | AD5273BRJZ1-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL 1K 64POS SOT23 |
| 標準包裝： | 1 |
| 接片： | 64 |
| 電阻（歐姆）： | 1k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 標準包裝 |
| 其它名稱： | AD5273BRJZ1-REEL7DKR |
AD5273
Rev. H | Page 19 of 24
APPLICATIONS INFORMATION
DAC
It is common to buffer the output of the digital potentiometer as
a DAC. The buffer minimizes the load dependence and delivers
higher current to the load, if needed.
GND
VIN
VOUT
1U1
5V
2
3
VO
AD8601
5V
A
W
B
ADR03
U3
AD5273
U2
03224-046
Figure 46. Programmable Voltage Reference (DAC)
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
For applications that require high current adjustment, such as a
laser diode driver or tunable laser, consider a booster voltage
source, as shown in Figure 47.
+V
W
SIGNAL
CC
RBIAS
LD
VIN
A
B
VOUT
U1
AD5273
U3 2N7002
AD8601
U2
–V
IL
03
22
4-
04
7
Figure 47. Programmable Booster Voltage Source
In this circuit, the inverting input of the op amp forces the
VOUT to be equal to the wiper voltage set by the digital potenti-
ometer. The load current is then delivered by the supply via the
N-Channel FET, N1. N1 power handling must be adequate to
dissipate (VIN VOUT) × IL power. This circuit can source a max-
imum of 100 mA with a 5 V supply. For precision applications,
can be applied at Terminal A of the digital potentiometer.
PROGRAMMABLE CURRENT SOURCE
A programmable current source can be implemented with the
circuit shown in Figure 48. The load current is the voltage across
Terminal B to Terminal W of the AD5273 divided by RS. At zero
scale, Terminal A of the AD5273 is 2.048 V, which makes the
wiper voltage clamped at ground potential. Depending on the
load, Equation 5 is therefore valid only at certain codes. For
example, when the compliance voltage, VL, equals half of VREF,
the current can be programmed from midscale to full scale of
the AD5273.
IL
GND
VS
2U1
5V
4
6
3
SLEEP
0V TO ...
OUPUT
REF191
C1
1F
B
A
W
RS
102
100
RL
VL
–2.048 + VL
–5V
OP1177
+5V
V+
V–
U2
U3
AD5273
03
224
-04
8
Figure 48. Programmable Current Source
(
)
63
32
|
64
/
≤
×
=
D
R
D
V
I
S
REF
L
(5)
GAIN CONTROL COMPENSATION
As shown in Figure 49, the digital potentiometers are
commonly used in gain controls or sensor transimpedance
amplifier signal conditioning applications.
U1
C2
4.7pF
A
B
W
VO
VI
C1
R1
47k
Ω
R2
100k
Ω
03224-049
Figure 49. Typical Noninverting Gain Amplifier
In both applications, one of the digital potentiometer terminals
is connected to the op amp inverting node with finite terminal
capacitance, C1. It introduces a zero for the 1 βo term with
20 dB/dec, whereas a typical op amp GBP has 20 dB/dec
characteristics. A large R2 and finite C1 can cause this zero’s
frequency to fall well below the crossover frequency. Therefore,
the rate of closure becomes 40 dB/dec and the system has a 0°
phase margin at the crossover frequency. The output may ring,
or in the worst case, oscillate when the input is a step function.
Similarly, it is also likely to ring when switching between two
gain values because this is equivalent to a step change at the
input. To reduce the effect of C1, users should also configure
Terminal B or Terminal A rather than Terminal W at the
inverting node.
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