參數(shù)資料
型號: AD5272BRMZ-20-RL7
廠商: Analog Devices Inc
文件頁數(shù): 11/28頁
文件大?。?/td> 0K
描述: IC DGTL POT 1024POS 20K 10MSOP
設(shè)計資源: Compact, Low Cost, 5 V, Variable Gain, Noninverting Amplifier Using AD5270/2 and AD8615 (CN0161)
Compact, Low Cost, 5 V, Variable Gain, Inverting Amplifier Using AD5270/2 and AD8615(CN0168)
標準包裝: 1
接片: 1024
電阻(歐姆): 20k
電路數(shù): 1
溫度系數(shù): 標準值 5 ppm/°C
存儲器類型: 非易失
接口: I²C
電源電壓: 2.7 V ~ 5.5 V,±2.5 V ~ 2.75 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 標準包裝
其它名稱: AD5272BRMZ-20-RL7DKR
Data Sheet
AD5272/AD5274
Rev. D | Page 19 of 28
WRITE OPERATION
It is possible to write data for the RDAC register or the control
register. When writing to the AD5272/AD5274, the user must
begin with a start command followed by an address byte (R/W
= 0), after which the AD5272/AD5274 acknowledges that it is
prepared to receive data by pulling SDA low.
Two bytes of data are then written to the RDAC, the most
significant byte followed by the least significant byte; both of
these data bytes are acknowledged by the AD5272/AD5274. A
stop condition follows. The write operations for the AD5272/
AD5274 are shown in Figure 43.
A repeated write function gives the user flexibility to update the
device a number of times after addressing the part only once, as
shown in Figure 44.
SCL
SDA
START BY
MASTER
ACK. BY
AD5272/AD5274
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
MOST SIGNIFICANT DATA BYTE
FRAME 3
LEAST SIGNIFICANT DATA BYTE
SCL (CONTINUED)
SDA (CONTINUED)
ACK. BY
AD5272/AD5274
ACK. BY
AD5272/AD5274
STOP BY
MASTER
0
19
1
99
9
1
01
1
A1
A0
0
C3
C2
C1
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0
80
76
-00
5
Figure 43. Write Command
0
80
76
-00
6
SCL
SDA
START BY
MASTER
FRAME 2
MOST SIGNIFICANT DATA BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
0
19
1
99
9
1
0
1
A1
A0
R/W
0
C3
C2
C1
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 3
LEAST SIGNIFICANT DATA BYTE
SCL (CONTINUED)
SDA (CONTINUED)
STOP BY
MASTER
1
99
D7
D6
D5
D4
D3
D2
D1
D0
(CONTINUED)
FRAME 5
LEAST SIGNIFICANT DATA BYTE
1
99
0
C3C2C1
C0
D9
D8
FRAME 4
MOST SIGNIFICANT DATA BYTE
SCL
SDA
ACK. BY
AD5272
2/AD5274
ACK. BY
AD5272
2/AD5274
ACK. BY
AD5272
2/AD5274
ACK. BY
AD5272
2/AD5274
ACK. BY
AD5272
2/AD5274
Figure 44. Multiple Write
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