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參數(shù)資料
| 型號(hào)： | AD5263BRUZ200 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT QUAD 200K 256POS 24-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 接片： | 256 |
| 電阻（歐姆）： | 200k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 30 ppm/°C |
| 存儲(chǔ)器類型： | 易失 |
| 接口： | I²C，SPI（芯片選擇，設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V，5 V ~ 15 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 787 (CN2011-ZH PDF) |
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AD5263
Data Sheet
Rev. F | Page 22 of 28
VLOGIC POWER SUPPLY
The AD5263 is capable of operating at high voltages beyond the
internal logic levels, which are limited to operation at 5 V. As a
result, VL always needs to be tied to a separate 2.7 V to 5.5 V source
to ensure proper digital signal levels. Logic levels must be limited to
VL, regardless of VDD. In addition, VL should always be less than
or equal to VDD.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 F to 0.1 F ceramic
disc or chip capacitors. Low ESR 1 F to 10 F tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 55). Notice the digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.
03142-
055
GND
VSS
VDD
AD5263
VSS
VDD
C1
0.1F
C2
0.1F
C3
10F
C4
10F
+
Figure 55. Power Supply Bypassing
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive loads
dominate the ac characteristics of the RDACs. Configured as a
potentiometer divider, the –3 dB bandwidth of the AD5263 (20 k
resistor) measures 300 kHz at half scale. Figure 22 provides the
large signal BODE plot characteristics of the three available
resistor versions: 20 k, 50 k, and 200 k. A parasitic simulation
model is shown in Figure 56. The following code provides a
macro model net list for the 20 k RDAC.
03142-
069
20k
CA
W
25pF
RDAC
A
B
CB
CW
25pF
55pF
Figure 56. RDAC Circuit Simulation Model for RDAC = 20 k
Listing 1. Macro Model Net List for RDAC
.PARAM D=256, RDAC=20E3
*
.SUBCKT DPOT (A,W,B)
*
CA
A
0
25E-12
RWA
A
W
{(1-D/256)*RDAC+60}
CW
W
0
55E-12
RWB
W
B
{D/256*RDAC+60}
CB
B
0
25E-12
*
.ENDS DPOT
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