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| 型號： | AD5259EVAL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5259 DGTL POT |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 已用 IC / 零件： | AD5259 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD5259BCPZ5-R7TR-ND - IC POT DGTL 5K 256POS 10LFCSP AD5259BCPZ50-R7TR-ND - IC POT DGTL 50K 256POS 10LFCSP AD5259BCPZ10-R7TR-ND - IC POT DGTL 10K 256POS 10LFCSP AD5259BCPZ100-R7TR-ND - IC POT DGTL 100K 256POS 10LFCSP AD5259BRMZ5-ND - IC POT DGTL 5K 256POS 10-MSOP AD5259BRMZ50-ND - IC POT DGTL 50K 256POS 10-MSOP AD5259BRMZ5-R7-ND - IC POT DGTL 5K 256POS 10MSOP AD5259BRMZ100-R7-ND - IC POT DGTL 100K 256POS 10MSOP AD5259BRMZ10-R7-ND - IC POT DGTL 10K 256POS 10MSOP AD5259BRMZ50-R7-ND - IC POT DGTL 50K 256POS 10MSOP 更多... |
Data Sheet
AD5259
Rev. C | Page 5 of 24
TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; 40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
I2C INTERFACE TIMING
CHARACTERISTICS1
SCL Clock Frequency
fSCL
0
400
kHz
tBUF Bus Free Time Between Stop
and Start
t1
1.3
μs
tHD;STA Hold Time (Repeated Start)
t2
After this period, the first clock pulse is
generated.
0.6
μs
tLOW Low Period of SCL Clock
t3
1.3
μs
tHIGH High Period of SCL Clock
t4
0.6
μs
tSU;STA Setup Time for Repeated
Start Condition
t5
0.6
μs
tHD;DAT Data Hold Time
t6
0
0.9
μs
tSU;DAT Data Setup Time
t7
100
ns
tF Fall Time of Both SDA and
SCL Signals
t8
300
ns
tR Rise Time of Both SDA and
SCL Signals
t9
300
ns
tSU;STO Setup Time for Stop Condition
t10
0.6
μs
EEPROM Data Storing Time
tEEMEM_STORE
26
ms
EEPROM Data Restoring Time at
Power On2
tEEMEM_RESTORE1
VDD rise time dependent. Measure without
decoupling capacitors at VDD and GND.
300
μs
EEPROM Data Restoring Time upon
Restore Command2
tEEMEM_RESTORE2
VDD = 5 V.
300
μs
EEPROM Data Rewritable Time3
tEEMEM_REWRITE
540
μs
FLASH/EE MEMORY RELIABILITY
100
700
kCycles
Data Retention5
100
Years
1 Standard I2C mode operation guaranteed by design.
2 During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
3 Delay time after power-on PRESET prior to writing new EEPROM data.
4 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +125°C; typical endurance at +25°C is 700,000 cycles.
5 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature.
05026-004
t1
t2
t3
t8
t9
t6
t4
t7
t5
t2
t10
PS
S
SCL
SDA
P
Figure 4. I2C Interface Timing Diagram
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