- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗9280 > AD5253BRU1 (Analog Devices Inc)IC DGTL POT QUAD 1K I2C 20-TSSOP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AD5253BRU1 |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 16/32闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DGTL POT QUAD 1K I2C 20-TSSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 75 |
| 鎺ョ墖锛� | 64 |
| 闆婚樆锛堟瓙濮嗭級锛� | 1k |
| 闆昏矾鏁�(sh霉)锛� | 4 |
| 婧害绯绘暩(sh霉)锛� | 妯�(bi膩o)婧�(zh菙n)鍊� 650 ppm/°C |
| 瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闈炴槗澶� |
| 鎺ュ彛锛� | I²C锛堣ō(sh猫)鍌欎綅鍧€锛� |
| 闆绘簮闆诲锛� | 2.7 V ~ 5.5 V锛�±2.25 V ~ 2.75 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 20-TSSOP锛�0.173"锛�4.40mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 20-TSSOP |
| 鍖呰锛� | 绠′欢 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�鐣�(d膩ng)鍓嶇16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�
Data Sheet
AD5253/AD5254
Rev. C | Page 23 of 32
03824-0-038
+5V
R1
AD1
AD0
N1
4
2
4
+5V
R2X
AD1
AD0
N2X
+5
P2Y
P3X
R3X
R3Y
N3Y
AD1
AD0
AD1
AD0
4
+5V
P4
R4
+5V
2
4
DECODER
4
2
4
DECODER
4
2
4
DECODER
4
2
4
DECODER
Figure 38. Four Devices with AD1 and AD0 of 00
TERMINAL VOLTAGE OPERATION RANGE
The AD5253/AD5254 are designed with internal ESD diodes
for protection; these diodes also set the boundaries for the
terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed VDD are
clamped by the forward-biased diode. Similarly, negative signals
on Terminal A, Terminal B, or Terminal W that are more
users should not operate VAB, VWA, and VWB to be higher than
the voltage across VDD to VSS, but VAB, VWA, and VWB have no
polarity constraint.
03824-0-039
VDD
A
W
B
VSS
Figure 39. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP AND POWER-DOWN SEQUENCES
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (Figure 39), it is
important to power VDD/VSS before applying any voltage to
these terminals. Otherwise, the diodes are forward biased such
that VDD/VSS are powered unintentionally and may affect the
user鈥檚 circuit. Similarly, VDD/VSS should be powered down last.
The ideal power-up sequence is in the following order: GND,
VDD, VSS, digital inputs, and VA/VB/VW. The order of powering
VA, VB, VW, and the digital inputs is not important, as long as
they are powered after VDD/VSS.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to employ a compact, minimum
lead-length layout design. The leads to the input should be as
direct as possible, with a minimum conductor length. Ground
paths should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors. Low equivalent series resistance (ESR)
1 渭F to 10 渭F tantalum or electrolytic capacitors should be
applied at the supplies to minimize any transient disturbance
and filter low frequency ripple. Figure 40 illustrates the basic
supply-bypassing configuration for the AD5253/AD5254.
03824-0-040
VDD
VSS
GND
C3
AD5253/AD5254
C4
C1
C2
10
F
10
F
0.1
F
0.1
F
Figure 40. Power Supply-Bypassing Configuration
The ground pin of the AD5253/AD5254 is used primarily as a
digital ground reference. To minimize the digital ground
bounce, the AD5253/AD5254 ground terminal should be joined
remotely to the common ground (see Figure 40).
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MS27467P17B6P | CONN PLUG 6POS STRAIGHT W/PINS |
| GTC06CF-24-6S | CONN PLUG 8POS STRAIGHT W/SCKT |
| DS1135U-10+T&R | IC DELAY LINE 10NS 8-USOP |
| MS27484T24B35PC | CONN PLUG 128POS STRAIGHT W/PINS |
| AD5253BRUZ1 | IC POT DGTL QUAD 1K I2C 20TSSOP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AD5253BRU10 | 鍔熻兘鎻忚堪:IC DGTL POT QUAD 10K I2C 20TSSOP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:3,000 绯诲垪:DPP 鎺ョ墖:32 闆婚樆锛堟瓙濮嗭級:10k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� 300 ppm/°C 瀛樺劜(ch菙)鍣ㄩ鍨�:闈炴槗澶� 鎺ュ彛:3 绶氫覆琛岋紙鑺墖閬告搰锛岄仦澧�锛屽/娓涳級 闆绘簮闆诲:2.5 V ~ 6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-WFDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-TDFN锛�2x3锛� 鍖呰:甯跺嵎 (TR) |
| AD5253BRU100 | 鍔熻兘鎻忚堪:IC DGTL POT QUAD 100K 20-TSSOP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:3,000 绯诲垪:DPP 鎺ョ墖:32 闆婚樆锛堟瓙濮嗭級:10k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� 300 ppm/°C 瀛樺劜(ch菙)鍣ㄩ鍨�:闈炴槗澶� 鎺ュ彛:3 绶氫覆琛岋紙鑺墖閬告搰锛岄仦澧�锛屽/娓涳級 闆绘簮闆诲:2.5 V ~ 6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-WFDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-TDFN锛�2x3锛� 鍖呰:甯跺嵎 (TR) |
| AD5253BRU100-RL7 | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:Digital Potentiometer 64POS 100KOhm Quad 20-Pin TSSOP T/R 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:DGTL POTENTIOMETER 64POS 100KOHM QUAD 20TSSOP - Tape and Reel |
| AD5253BRU10-RL7 | 鍔熻兘鎻忚堪:IC DGTL POT QUAD 10K 20-TSSOP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:3,000 绯诲垪:DPP 鎺ョ墖:32 闆婚樆锛堟瓙濮嗭級:10k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� 300 ppm/°C 瀛樺劜(ch菙)鍣ㄩ鍨�:闈炴槗澶� 鎺ュ彛:3 绶氫覆琛岋紙鑺墖閬告搰锛岄仦澧�锛屽/娓涳級 闆绘簮闆诲:2.5 V ~ 6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-WFDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-TDFN锛�2x3锛� 鍖呰:甯跺嵎 (TR) |
| AD5253BRU1-RL7 | 鍔熻兘鎻忚堪:IC DGTL POT QUAD 1K 20-TSSOP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:3,000 绯诲垪:DPP 鎺ョ墖:32 闆婚樆锛堟瓙濮嗭級:10k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� 300 ppm/°C 瀛樺劜(ch菙)鍣ㄩ鍨�:闈炴槗澶� 鎺ュ彛:3 绶氫覆琛岋紙鑺墖閬告搰锛岄仦澧烇紝澧�/娓涳級 闆绘簮闆诲:2.5 V ~ 6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-WFDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-TDFN锛�2x3锛� 鍖呰:甯跺嵎 (TR) |
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
