參數資料
| 型號： | AD5252BRUZ1-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 25/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT DUAL 1K 14-TSSOP |
| 標準包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 1k |
| 電路數： | 2 |
| 溫度系數： | 標準值 650 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
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AD5251/AD5252
Data Sheet
Rev. D | Page 6 of 28
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
POWER SUPPLIES
Single-Supply Power Range
V
DD
V
SS = 0 V
2.7
5.5
V
Dual-Supply Power Range
V
DD/VSS
±2.25
±2.75
V
Positive Supply Current
I
DD
V
IH = VDD or VIL = GND
5
15
A
Negative Supply Current
I
SS
V
IH = VDD or VIL = GND, VDD = 2.5 V,
V
SS = 2.5 V
5
15
A
EEMEM Data Storing Mode
Current
I
DD_STORE
V
IH = VDD or VIL = GND, TA = 0°C to 105°C
35
mA
EEMEM Data Restoring Mode
Current6
I
DD_RESTORE
V
IH = VDD or VIL = GND, TA = 0°C to 105°C
2.5
mA
Power Dissipation7
P
DISS
V
IH = VDD = 5 V or VIL = GND
0.075
mW
Power Supply Sensitivity
PSS
ΔV
DD = 5 V ± 10%
0.005
+0.002
+0.005
%/%
ΔV
DD = 3 V ± 10%
0.010
+0.002
+0.010
%/%
–3 dB Bandwidth
BW
R
AB = 10 k/50 k/100 k
400/80/40
kHz
Total Harmonic Distortion
THD
W
V
A = 1 V rms, VB = 0 V, f = 1 kHz
0.05
%
V
W Settling Time
t
S
V
A = VDD, VB = 0 V,
R
AB = 10 k/50 k/100 k
1.5/7/14
s
Resistor Noise Voltage
e
N_WB
R
AB = 10 k/50 k/100 k,
code = midscale, f = 1 kHz
(thermal noise only)
9/20/29
nV/√Hz
Digital Crosstalk
C
T
V
A = VDD, VB = 0 V, measure VW with
adjacent RDAC making full-scale
change
80
dB
Analog Coupling
C
AT
Signal input at A1 and measure
output at W3, f = 1 kHz
72
dB
1 Typical values represent average readings at 25°C and V
DD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the
relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 k version at VDD = 2.7 V,
IW = VDD/R for both VDD = 3 V and VDD = 5 V.
3 INL and DNL are measured at V
W with the RDAC configured as a potentiometer divider, similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 Command 0 NOP should be activated after Command 1 to minimize I
DD_READ current consumption.
7 P
DISS is calculated from IDD × VDD = 5 V.
8 All dynamic characteristics use V
DD = 5 V.
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